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Statements

Subject Item
n2:RIV%2F46747885%3A24220%2F13%3A%230002863%21RIV14-MSM-24220___
rdf:type
n6:Vysledek skos:Concept
rdfs:seeAlso
http://apps.webofknowledge.com/full_record.do?product=UA&search_mode=GeneralSearch&qid=9&SID=V2ZZlanTQqUyFdhYYcD&page=1&doc=1
dcterms:description
This paper presents a design flow that allows relocation of reconfigurable modules on Xilinx FPGAs using dynamic partial reconfiguration (DPR). Relocation of these modules is performed without requirements of re-implementing the design. The article describes the relocation procedure based on modifications of major address of the partial configuration bitstream. This approach allows using single partial bitstream for multiple areas in FPGA device. It reduces a number of partial bitstreams stored in memory, saves the implementation time and it can increase dependability of the system. The proposed flow is demonstrated on a simple example with multiplier and adder locations mutually exchanged. This paper presents a design flow that allows relocation of reconfigurable modules on Xilinx FPGAs using dynamic partial reconfiguration (DPR). Relocation of these modules is performed without requirements of re-implementing the design. The article describes the relocation procedure based on modifications of major address of the partial configuration bitstream. This approach allows using single partial bitstream for multiple areas in FPGA device. It reduces a number of partial bitstreams stored in memory, saves the implementation time and it can increase dependability of the system. The proposed flow is demonstrated on a simple example with multiplier and adder locations mutually exchanged.
dcterms:title
Relocation of reconfigurable modules on Xilinx FPGA Relocation of reconfigurable modules on Xilinx FPGA
skos:prefLabel
Relocation of reconfigurable modules on Xilinx FPGA Relocation of reconfigurable modules on Xilinx FPGA
skos:notation
RIV/46747885:24220/13:#0002863!RIV14-MSM-24220___
n6:predkladatel
n16:orjk%3A24220
n3:aktivita
n7:S n7:P
n3:aktivity
P(LD13019), S
n3:dodaniDat
n11:2014
n3:domaciTvurceVysledku
n5:5151600 n5:9570748 n5:4412281
n3:druhVysledku
n12:D
n3:duvernostUdaju
n23:S
n3:entitaPredkladatele
n22:predkladatel
n3:idSjednocenehoVysledku
102299
n3:idVysledku
RIV/46747885:24220/13:#0002863
n3:jazykVysledku
n15:eng
n3:klicovaSlova
FPGA partial reconfiguration
n3:klicoveSlovo
n21:FPGA%20partial%20reconfiguration
n3:kontrolniKodProRIV
[4B670C6E198C]
n3:mistoKonaniAkce
Karlovy Vary; Czech Republic
n3:nazevZdroje
16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013
n3:obor
n14:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n4:LD13019
n3:rokUplatneniVysledku
n11:2013
n3:tvurceVysledku
Drahoňovský, Tomáš Novák, Ondřej Rozkovec, Martin
n3:typAkce
n20:WRD
n3:zahajeniAkce
2013-01-01+01:00
s:numberOfPages
6
n10:doi
10.1109/DDECS.2013.6549812
n24:hasPublisher
IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
n17:isbn
978-1-4673-6135-4
n18:organizacniJednotka
24220