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Statements

Subject Item
n2:RIV%2F46747885%3A24220%2F12%3A%230002019%21RIV13-MSM-24220___
rdf:type
n11:Vysledek skos:Concept
rdfs:seeAlso
http://apps.webofknowledge.com/full_record.do?product=WOS&search_mode=GeneralSearch&qid=10&SID=W1INN4fIFD5m8h3IIim&page=1&doc=2
dcterms:description
In this paper we evaluate the application dependent FPGA (Field Programmable Gate Array) test method which uses an ASIC BIST (Application Specific Integrated Circuit Built-in Self-Test) techniques and tools and efficiently utilizes the properties of nowadays FPGA devices, such as the partial runtime reconfiguration. The method splits the tested circuit and then uses partial reconfiguration to change the role of the partitioned modules, which may act as testers or as response analyzers. Circuit partitions are translated to an ATPG (Automatic Test Pattern Generator) readable format and the deterministic test vectors are generated. The compression tool is used to compress test patterns, thus it is not required to create additional test access interfaces or to use multiple reconfigurations. We show that the usage of the method reduces test time and memory requirements and it leads to good test coverage results. Each step of the design flow is described and evaluated in detail as well as the experimental results and the hardware. In this paper we evaluate the application dependent FPGA (Field Programmable Gate Array) test method which uses an ASIC BIST (Application Specific Integrated Circuit Built-in Self-Test) techniques and tools and efficiently utilizes the properties of nowadays FPGA devices, such as the partial runtime reconfiguration. The method splits the tested circuit and then uses partial reconfiguration to change the role of the partitioned modules, which may act as testers or as response analyzers. Circuit partitions are translated to an ATPG (Automatic Test Pattern Generator) readable format and the deterministic test vectors are generated. The compression tool is used to compress test patterns, thus it is not required to create additional test access interfaces or to use multiple reconfigurations. We show that the usage of the method reduces test time and memory requirements and it leads to good test coverage results. Each step of the design flow is described and evaluated in detail as well as the experimental results and the hardware.
dcterms:title
An evaluation of the application dependent FPGA test method An evaluation of the application dependent FPGA test method
skos:prefLabel
An evaluation of the application dependent FPGA test method An evaluation of the application dependent FPGA test method
skos:notation
RIV/46747885:24220/12:#0002019!RIV13-MSM-24220___
n11:predkladatel
n17:orjk%3A24220
n4:aktivita
n14:S
n4:aktivity
S
n4:dodaniDat
n13:2013
n4:domaciTvurceVysledku
n8:4412281 n8:5144795 n8:9570748
n4:druhVysledku
n21:D
n4:duvernostUdaju
n12:S
n4:entitaPredkladatele
n7:predkladatel
n4:idSjednocenehoVysledku
121955
n4:idVysledku
RIV/46747885:24220/12:#0002019
n4:jazykVysledku
n18:eng
n4:klicovaSlova
Field programmable gate arrays
n4:klicoveSlovo
n22:Field%20programmable%20gate%20arrays
n4:kontrolniKodProRIV
[80413C6989CD]
n4:mistoKonaniAkce
Tallinn, ESTONIA
n4:nazevZdroje
Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012
n4:obor
n6:JC
n4:pocetDomacichTvurcuVysledku
3
n4:pocetTvurcuVysledku
3
n4:rokUplatneniVysledku
n13:2012
n4:tvurceVysledku
Jeníček, Jiří Novák, Ondřej Rozkovec, Martin
n4:typAkce
n15:WRD
n4:wos
000312905700011
n4:zahajeniAkce
2012-04-18+02:00
s:numberOfPages
4
n19:doi
10.1109/DDECS.2012.6219017
n20:hasPublisher
IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
n10:isbn
978-1-4673-1187-8
n16:organizacniJednotka
24220