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Statements

Subject Item
n2:RIV%2F46747885%3A24220%2F12%3A%230002014%21RIV13-MSM-24220___
rdf:type
n15:Vysledek skos:Concept
rdfs:seeAlso
http://www.scopus.com
dcterms:description
The reliability issue, including aging processes in modern devices with very fine structures and utilizing programmable technologies, being applied in high-performance or dependable systems in various safety, automotive or space applications, is sometimes very difficult to predict, measure or watch. The task is well-mastered in the world of ASIC, the situation is slightly different for FPGA devices. Modern FPGA devices incorporate number of true dual-port memory blocks with 8-T cells, hence offering new options. However, such blocks are typically used for data storage and processing purposes. This paper presents a new way of utilization of the RAM block (BRAM) for the delay fault detection purposes. The BRAM and a simple controller log risky transitions or delay fault events and may positively affect the overall reliability of the device as well as all the system. The reliability issue, including aging processes in modern devices with very fine structures and utilizing programmable technologies, being applied in high-performance or dependable systems in various safety, automotive or space applications, is sometimes very difficult to predict, measure or watch. The task is well-mastered in the world of ASIC, the situation is slightly different for FPGA devices. Modern FPGA devices incorporate number of true dual-port memory blocks with 8-T cells, hence offering new options. However, such blocks are typically used for data storage and processing purposes. This paper presents a new way of utilization of the RAM block (BRAM) for the delay fault detection purposes. The BRAM and a simple controller log risky transitions or delay fault events and may positively affect the overall reliability of the device as well as all the system.
dcterms:title
Delay-fault run-time XOR-less aging detection unit using BRAM in modern FPGAs Delay-fault run-time XOR-less aging detection unit using BRAM in modern FPGAs
skos:prefLabel
Delay-fault run-time XOR-less aging detection unit using BRAM in modern FPGAs Delay-fault run-time XOR-less aging detection unit using BRAM in modern FPGAs
skos:notation
RIV/46747885:24220/12:#0002014!RIV13-MSM-24220___
n15:predkladatel
n16:orjk%3A24220
n4:aktivita
n8:S
n4:aktivity
S
n4:dodaniDat
n11:2013
n4:domaciTvurceVysledku
n7:8619158 n7:7390742
n4:druhVysledku
n14:D
n4:duvernostUdaju
n5:S
n4:entitaPredkladatele
n9:predkladatel
n4:idSjednocenehoVysledku
129962
n4:idVysledku
RIV/46747885:24220/12:#0002014
n4:jazykVysledku
n18:eng
n4:klicovaSlova
Delay fault
n4:klicoveSlovo
n22:Delay%20fault
n4:kontrolniKodProRIV
[11FC5A4AD634]
n4:mistoKonaniAkce
Tallinn
n4:nazevZdroje
Proceedings of the Biennial Baltic Electronics Conference, BEC
n4:obor
n10:JC
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
2
n4:rokUplatneniVysledku
n11:2012
n4:tvurceVysledku
Pfeifer, Petr Plíva, Zdeněk
n4:typAkce
n20:WRD
n4:zahajeniAkce
2012-10-03+02:00
s:issn
1736-3705
s:numberOfPages
4
n21:doi
10.1109/BEC.2012.6376820
n19:hasPublisher
Neuveden
n17:isbn
978-1-4673-2775-6
n13:organizacniJednotka
24220