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Statements

Subject Item
n2:RIV%2F46747885%3A24220%2F01%3A00000024%21RIV%2F2002%2FMSM%2F242202%2FN
rdf:type
skos:Concept n16:Vysledek
dcterms:description
The article describes Low Hardware Overhead Deterministic Logic Test Pattern Generator The article describes Low Hardware Overhead Deterministic Logic Test Pattern Generator
dcterms:title
Low Hardware Overhead Deterministic Logic Test Pattern Generator Low Hardware Overhead Deterministic Logic Test Pattern Generator
skos:prefLabel
Low Hardware Overhead Deterministic Logic Test Pattern Generator Low Hardware Overhead Deterministic Logic Test Pattern Generator
skos:notation
RIV/46747885:24220/01:00000024!RIV/2002/MSM/242202/N
n3:strany
137-140
n3:aktivita
n10:P n10:Z
n3:aktivity
P(GA102/01/0566), Z(MSM 242200002)
n3:dodaniDat
n4:2002
n3:domaciTvurceVysledku
n13:9570748 n13:5893372
n3:druhVysledku
n12:D
n3:duvernostUdaju
n22:S
n3:entitaPredkladatele
n21:predkladatel
n3:idSjednocenehoVysledku
685568
n3:idVysledku
RIV/46747885:24220/01:00000024
n3:jazykVysledku
n11:eng
n3:klicovaSlova
%22BIST; diagnostics; test pattern generation%22
n3:klicoveSlovo
n9:diagnostics n9:%2522BIST n9:test%20pattern%20generation%2522
n3:kontrolniKodProRIV
[D8406779D4DE]
n3:mistoKonaniAkce
Toulouse, France
n3:mistoVydani
Toulouse, France
n3:nazevZdroje
Proc of ECM2S
n3:obor
n19:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:pocetUcastnikuAkce
0
n3:pocetZahranicnichUcastnikuAkce
0
n3:projekt
n15:GA102%2F01%2F0566
n3:rokUplatneniVysledku
n4:2001
n3:tvurceVysledku
Nosek, Jiří Novák, Ondřej
n3:typAkce
n14:WRD
n3:zahajeniAkce
2001-05-30+02:00
n3:zamer
n7:MSM%20242200002
s:numberOfPages
4
n18:hasPublisher
Université Paul Sabatier Toulouse
n17:isbn
80-7083-444-7
n20:organizacniJednotka
24220