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Statements

Subject Item
n2:RIV%2F46747885%3A24220%2F00%3A00000031%21RIV%2F2001%2FMSM%2F242201%2FN
rdf:type
n6:Vysledek skos:Concept
dcterms:description
An Efficient Deterministic test Pattern Compaction Scheme Using Modified IC Scan Chain An Efficient Deterministic test Pattern Compaction Scheme Using Modified IC Scan Chain
dcterms:title
Optimised Hardware Test Pattern Generator for BIST Optimised Hardware Test Pattern Generator for BIST
skos:prefLabel
Optimised Hardware Test Pattern Generator for BIST Optimised Hardware Test Pattern Generator for BIST
skos:notation
RIV/46747885:24220/00:00000031!RIV/2001/MSM/242201/N
n3:strany
205
n3:aktivita
n16:P n16:Z
n3:aktivity
P(VS96006), Z(MSM 242200002)
n3:dodaniDat
n11:2001
n3:domaciTvurceVysledku
Novák, Ondrej
n3:druhVysledku
n7:D
n3:duvernostUdaju
n20:S
n3:entitaPredkladatele
n17:predkladatel
n3:idSjednocenehoVysledku
720736
n3:idVysledku
RIV/46747885:24220/00:00000031
n3:jazykVysledku
n19:eng
n3:klicovaSlova
IC design
n3:klicoveSlovo
n18:IC%20design
n3:kontrolniKodProRIV
[A9CE58409CC0]
n3:mistoVydani
Slovensko
n3:nazevZdroje
Proc. of Design and Diagnostics of Electronics Circuits and System Workshop
n3:obor
n14:JA
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n4:VS96006
n3:rokUplatneniVysledku
n11:2000
n3:tvurceVysledku
Novák, Ondrej
n3:zamer
n10:MSM%20242200002
s:numberOfPages
4
n9:hasPublisher
Slovenská akadémia vied
n15:isbn
80-968320-
n12:organizacniJednotka
24220