This HTML5 document contains 44 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
n11http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n16http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F00216305%3A26230%2F14%3APU112083%21RIV15-GA0-26230___/
n18http://localhost/temp/predkladatel/
n15http://purl.org/net/nknouf/ns/bibtex#
n22http://linked.opendata.cz/resource/domain/vavai/projekt/
n17http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n14http://linked.opendata.cz/ontology/domain/vavai/
n10https://schema.org/
shttp://schema.org/
n4http://linked.opendata.cz/ontology/domain/vavai/riv/
rdfshttp://www.w3.org/2000/01/rdf-schema#
skoshttp://www.w3.org/2004/02/skos/core#
n9http://bibframe.org/vocab/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n13http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n19http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n21http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n5http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n20http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n8http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n12http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F14%3APU112083%21RIV15-GA0-26230___
rdf:type
skos:Concept n14:Vysledek
rdfs:seeAlso
http://dx.doi.org/10.1109/ICES.2014.7008716
dcterms:description
The aim of this paper is to introduce a new acceleratordeveloped to address the problem of evolutionary synthesisof digital circuits at transistor level. The proposed accelerator,based on recently introduced Xilinx Zynq platform, consists ofa discrete simulator implemented in programmable logic and anevolutionary algorithm running on a tightly coupled embeddedARM processor. The discrete simulator was introduced in order toachieve a good trade-off between the precision and performanceof the simulation of transistor-level circuits. The simulator isimplemented using the concept of virtual reconfigurable circuitand operates on multiple logic levels which enables to evaluate thebehavior of candidate transistor-level circuits at a reasonable levelof detail. In this work, the concept of virtual reconfigurable circuitwas extended to enable bidirectional data flow which representsthe basic feature of transistor level circuits. According to theexperimental evaluation, the proposed architecture speed The aim of this paper is to introduce a new acceleratordeveloped to address the problem of evolutionary synthesisof digital circuits at transistor level. The proposed accelerator,based on recently introduced Xilinx Zynq platform, consists ofa discrete simulator implemented in programmable logic and anevolutionary algorithm running on a tightly coupled embeddedARM processor. The discrete simulator was introduced in order toachieve a good trade-off between the precision and performanceof the simulation of transistor-level circuits. The simulator isimplemented using the concept of virtual reconfigurable circuitand operates on multiple logic levels which enables to evaluate thebehavior of candidate transistor-level circuits at a reasonable levelof detail. In this work, the concept of virtual reconfigurable circuitwas extended to enable bidirectional data flow which representsthe basic feature of transistor level circuits. According to theexperimental evaluation, the proposed architecture speed
dcterms:title
Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform
skos:prefLabel
Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform
skos:notation
RIV/00216305:26230/14:PU112083!RIV15-GA0-26230___
n4:aktivita
n21:P
n4:aktivity
P(GA14-04197S)
n4:dodaniDat
n12:2015
n4:domaciTvurceVysledku
n17:2599554 n17:6455719
n4:druhVysledku
n8:D
n4:duvernostUdaju
n19:S
n4:entitaPredkladatele
n16:predkladatel
n4:idSjednocenehoVysledku
1401
n4:idVysledku
RIV/00216305:26230/14:PU112083
n4:jazykVysledku
n5:eng
n4:klicovaSlova
Xilinx Zynq, transistor-level evolution, evolutionary design, combinational circuit
n4:klicoveSlovo
n13:transistor-level%20evolution n13:combinational%20circuit n13:Xilinx%20Zynq n13:evolutionary%20design
n4:kontrolniKodProRIV
[24681F5E9B60]
n4:mistoKonaniAkce
Orlando
n4:mistoVydani
Piscataway
n4:nazevZdroje
2014 IEEE International Conference on Evolvable Systems Proceedings
n4:obor
n20:IN
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
2
n4:projekt
n22:GA14-04197S
n4:rokUplatneniVysledku
n12:2014
n4:tvurceVysledku
Mrázek, Vojtěch Vašíček, Zdeněk
n4:typAkce
n11:WRD
n4:zahajeniAkce
2014-12-09+01:00
s:numberOfPages
8
n9:doi
10.1109/ICES.2014.7008716
n15:hasPublisher
Institute of Electrical and Electronics Engineers
n10:isbn
978-1-4799-4480-4
n18:organizacniJednotka
26230