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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F14%3APU112042%21RIV15-MSM-26230___
rdf:type
n7:Vysledek skos:Concept
dcterms:description
Regular expression matching is a time critical operation for any network security system. The NFA-Split is an efficient hardware architecture to match a large set of regular expressions at multigigabit speed with efficient FPGA logic utilization. Unfortunately, the matching speed is limited by processing only single byte in one clock cycle. Therefore, we propose new multi-stride NFA-Split architecture, which increases achievable throughput by processing multiple bytes per clock cycle. Moreover, we investigate efficiency of mapping DU to the FPGA logic and propose new optimizations of mapping NFA-Split architecture to the FPGA. These optimizations are able to reduce up to 71.85% of FPGA LUTs and up to 94.18% of BlockRAMs. Regular expression matching is a time critical operation for any network security system. The NFA-Split is an efficient hardware architecture to match a large set of regular expressions at multigigabit speed with efficient FPGA logic utilization. Unfortunately, the matching speed is limited by processing only single byte in one clock cycle. Therefore, we propose new multi-stride NFA-Split architecture, which increases achievable throughput by processing multiple bytes per clock cycle. Moreover, we investigate efficiency of mapping DU to the FPGA logic and propose new optimizations of mapping NFA-Split architecture to the FPGA. These optimizations are able to reduce up to 71.85% of FPGA LUTs and up to 94.18% of BlockRAMs.
dcterms:title
Multi-Stride NFA-Split Architecture for Regular Expression Matching Using FPGA Multi-Stride NFA-Split Architecture for Regular Expression Matching Using FPGA
skos:prefLabel
Multi-Stride NFA-Split Architecture for Regular Expression Matching Using FPGA Multi-Stride NFA-Split Architecture for Regular Expression Matching Using FPGA
skos:notation
RIV/00216305:26230/14:PU112042!RIV15-MSM-26230___
n4:aktivita
n15:S n15:P
n4:aktivity
P(ED1.1.00/02.0070), S
n4:dodaniDat
n5:2015
n4:domaciTvurceVysledku
n11:3991385 n11:9452591
n4:druhVysledku
n6:D
n4:duvernostUdaju
n19:S
n4:entitaPredkladatele
n13:predkladatel
n4:idSjednocenehoVysledku
31129
n4:idVysledku
RIV/00216305:26230/14:PU112042
n4:jazykVysledku
n9:eng
n4:klicovaSlova
NFA, FPGA, Regular Expression Matching
n4:klicoveSlovo
n16:FPGA n16:Regular%20Expression%20Matching n16:NFA
n4:kontrolniKodProRIV
[8E2B2B7702DA]
n4:mistoKonaniAkce
Telč
n4:mistoVydani
Brno
n4:nazevZdroje
Proceedings of the 9th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
n4:obor
n17:JC
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
2
n4:projekt
n21:ED1.1.00%2F02.0070
n4:rokUplatneniVysledku
n5:2014
n4:tvurceVysledku
Košař, Vlastimil Kořenek, Jan
n4:typAkce
n12:WRD
n4:zahajeniAkce
2014-10-17+02:00
s:numberOfPages
12
n20:hasPublisher
NOVPRESS s.r.o.
n8:isbn
978-80-214-5022-6
n18:organizacniJednotka
26230