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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F14%3APU111987%21RIV15-MSM-26230___
rdf:type
skos:Concept n19:Vysledek
dcterms:description
Recent growth in algorithmic trading has caused a demand for lowering the latency of systems for electronic trading. FPGA cards are widely used to reduce latency and accelerate market data processing. To create a low latency trading system, it is crucial to effectively build a representation of the market state (book) in hardware. Thus, we have designed a new hardware architecture, which updates the book with the best bid/offer prices based on the incoming messages from the exchange. For each message a corresponding financial instrument needs to be looked up and its record needs to be updated. Proposed architecture is utilizing cuckoo hashing for the book handling, which enables low latency symbol lookup and high memory utilization. In this paper we discuss a trade-off between lookup latency and memory utilization. With average latency of 253 ns the proposed architecture is able to handle 119 275 instruments while using only 144 Mbit QDR SRAM. Recent growth in algorithmic trading has caused a demand for lowering the latency of systems for electronic trading. FPGA cards are widely used to reduce latency and accelerate market data processing. To create a low latency trading system, it is crucial to effectively build a representation of the market state (book) in hardware. Thus, we have designed a new hardware architecture, which updates the book with the best bid/offer prices based on the incoming messages from the exchange. For each message a corresponding financial instrument needs to be looked up and its record needs to be updated. Proposed architecture is utilizing cuckoo hashing for the book handling, which enables low latency symbol lookup and high memory utilization. In this paper we discuss a trade-off between lookup latency and memory utilization. With average latency of 253 ns the proposed architecture is able to handle 119 275 instruments while using only 144 Mbit QDR SRAM.
dcterms:title
Low Latency Book Handling in FPGA for High Frequency Trading Low Latency Book Handling in FPGA for High Frequency Trading
skos:prefLabel
Low Latency Book Handling in FPGA for High Frequency Trading Low Latency Book Handling in FPGA for High Frequency Trading
skos:notation
RIV/00216305:26230/14:PU111987!RIV15-MSM-26230___
n3:aktivita
n5:S
n3:aktivity
S
n3:dodaniDat
n7:2015
n3:domaciTvurceVysledku
n11:9452591 n11:2088320
n3:druhVysledku
n16:D
n3:duvernostUdaju
n10:S
n3:entitaPredkladatele
n6:predkladatel
n3:idSjednocenehoVysledku
26673
n3:idVysledku
RIV/00216305:26230/14:PU111987
n3:jazykVysledku
n20:eng
n3:klicovaSlova
FPGA, Cuckoo hashing, HFT, High Frequency Trading,
n3:klicoveSlovo
n12:HFT n12:FPGA n12:High%20Frequency%20Trading n12:Cuckoo%20hashing
n3:kontrolniKodProRIV
[911D12F1E9D1]
n3:mistoKonaniAkce
Warsaw
n3:mistoVydani
Warszawa
n3:nazevZdroje
17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
n3:obor
n4:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:rokUplatneniVysledku
n7:2014
n3:tvurceVysledku
Dvořák, Milan Kořenek, Jan
n3:typAkce
n15:WRD
n3:zahajeniAkce
2014-04-23+02:00
s:numberOfPages
4
n14:hasPublisher
IEEE Computer Society
n18:isbn
978-1-4799-4558-0
n17:organizacniJednotka
26230