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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F14%3APU111928%21RIV15-MSM-26230___
rdf:type
skos:Concept n23:Vysledek
dcterms:description
The NFA-Split architecture is an efficient approach to the mapping of regular expressions to the FPGA. However, the NFA-Split architecture has some drawbacks. The most significant are the high time complexity due to usage of determinisation to detect simultaneously active states. The other one is in some cases high consumption of BRAMs. The paper presents solutions of those drawbacks. According to the results up to 39 times overall speedup of construction of the NFA-Split architecture was achieved. Reduction of utilized BRAMs is up to 97%. The NFA-Split architecture is an efficient approach to the mapping of regular expressions to the FPGA. However, the NFA-Split architecture has some drawbacks. The most significant are the high time complexity due to usage of determinisation to detect simultaneously active states. The other one is in some cases high consumption of BRAMs. The paper presents solutions of those drawbacks. According to the results up to 39 times overall speedup of construction of the NFA-Split architecture was achieved. Reduction of utilized BRAMs is up to 97%.
dcterms:title
On NFA-Split Architecture Optimizations On NFA-Split Architecture Optimizations
skos:prefLabel
On NFA-Split Architecture Optimizations On NFA-Split Architecture Optimizations
skos:notation
RIV/00216305:26230/14:PU111928!RIV15-MSM-26230___
n3:aktivita
n15:Z n15:S n15:P
n3:aktivity
P(ED1.1.00/02.0070), S, Z(MSM0021630528)
n3:dodaniDat
n5:2015
n3:domaciTvurceVysledku
n18:9452591 n18:3991385
n3:druhVysledku
n21:D
n3:duvernostUdaju
n10:S
n3:entitaPredkladatele
n4:predkladatel
n3:idSjednocenehoVysledku
34330
n3:idVysledku
RIV/00216305:26230/14:PU111928
n3:jazykVysledku
n20:eng
n3:klicovaSlova
Regular expressions, Pattern matching, FPGA, NFA
n3:klicoveSlovo
n6:FPGA n6:Regular%20expressions n6:NFA n6:Pattern%20matching
n3:kontrolniKodProRIV
[C85814B481B3]
n3:mistoKonaniAkce
Warsaw
n3:mistoVydani
Warsaw
n3:nazevZdroje
2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
n3:obor
n19:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n14:ED1.1.00%2F02.0070
n3:rokUplatneniVysledku
n5:2014
n3:tvurceVysledku
Košař, Vlastimil Kořenek, Jan
n3:typAkce
n11:WRD
n3:zahajeniAkce
2014-04-23+02:00
n3:zamer
n17:MSM0021630528
s:numberOfPages
4
n22:doi
10.1109/DDECS.2014.6868808
n12:hasPublisher
IEEE Computer Society
n8:isbn
978-1-4799-4558-0
n13:organizacniJednotka
26230