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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F14%3APU111908%21RIV15-GA0-26230___
rdf:type
skos:Concept n10:Vysledek
rdfs:seeAlso
http://dx.doi.org/10.1109/ICES.2014.7008726
dcterms:description
Field programmable gate arrays (FPGAs) are a popular platform for evolving digital circuits. FPGAs allow to be reconfigured partially which provides a natural way of establishing candidate solutions. Recent research focuses on the hardware implementation of evolutionary design platforms. Several approaches were developed for effective implementation of candidate solutions in FPGAs. In this paper a new mutation operator is proposed for evolutionary algorithms. The chromosome representing the candidate solution is mutated in such a way that only one configuration frame is required for establishing the mutated candidate solution in hardware. The experimental results confirmed that the reduced number of configuration frames and mutations at lower level of granularity ensure faster evolution, generation of more candidate solutions in a given time and solutions with better quality. Field programmable gate arrays (FPGAs) are a popular platform for evolving digital circuits. FPGAs allow to be reconfigured partially which provides a natural way of establishing candidate solutions. Recent research focuses on the hardware implementation of evolutionary design platforms. Several approaches were developed for effective implementation of candidate solutions in FPGAs. In this paper a new mutation operator is proposed for evolutionary algorithms. The chromosome representing the candidate solution is mutated in such a way that only one configuration frame is required for establishing the mutated candidate solution in hardware. The experimental results confirmed that the reduced number of configuration frames and mutations at lower level of granularity ensure faster evolution, generation of more candidate solutions in a given time and solutions with better quality.
dcterms:title
Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in Field Programmable Gate Arrays Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in Field Programmable Gate Arrays
skos:prefLabel
Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in Field Programmable Gate Arrays Evolutionary Digital Circuit Design with Fast Candidate Solution Establishment in Field Programmable Gate Arrays
skos:notation
RIV/00216305:26230/14:PU111908!RIV15-GA0-26230___
n3:aktivita
n5:P
n3:aktivity
P(GA14-04197S)
n3:dodaniDat
n12:2015
n3:domaciTvurceVysledku
Dobai, Roland n11:7173873
n3:druhVysledku
n18:D
n3:duvernostUdaju
n8:S
n3:entitaPredkladatele
n13:predkladatel
n3:idSjednocenehoVysledku
15599
n3:idVysledku
RIV/00216305:26230/14:PU111908
n3:jazykVysledku
n20:eng
n3:klicovaSlova
evolutionary design, mutation, reconfiguration, image filters, Zynq.
n3:klicoveSlovo
n4:Zynq. n4:reconfiguration n4:image%20filters n4:mutation n4:evolutionary%20design
n3:kontrolniKodProRIV
[41DE01E6E0AB]
n3:mistoKonaniAkce
Orlando
n3:mistoVydani
Piscataway
n3:nazevZdroje
2014 IEEE International Conference on Evolvable Systems Proceedings
n3:obor
n17:IN
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
4
n3:projekt
n14:GA14-04197S
n3:rokUplatneniVysledku
n12:2014
n3:tvurceVysledku
Torresen, Jim Glette, Kyrre Dobai, Roland Sekanina, Lukáš
n3:typAkce
n22:WRD
n3:zahajeniAkce
2014-12-09+01:00
s:numberOfPages
6
n23:doi
10.1109/ICES.2014.7008726
n16:hasPublisher
Institute of Electrical and Electronics Engineers
n15:isbn
978-1-4799-4480-4
n21:organizacniJednotka
26230