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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F13%3APU107071%21RIV14-MSM-26230___
rdf:type
skos:Concept n15:Vysledek
dcterms:description
Many algorithms have been proposed to accelerate regular expression matching via mapping of a nondeterministic finite automaton into a circuit implemented in an FPGA. These algorithms exploit unique features of the FPGA to achieve high throughput. On the other hand the FPGA poses a limit on the number of regular expressions by its limited resources. In this paper, we investigate applicability of NFA reduction techniques - a formal aparatus to reduce the number of states and transitions in NFA prior to its mapping into FPGA. The paper presents several NFA reduction techniques, each with a different reduction power and time complexity. The evaluation utilizes regular expressions from Snort and L7 decoder. The best NFA reduction algorithms achieve more than 66% reduction in the number of states for a Snort ftp module. Such a reduction translates directly into 66% LUT and FF saving in the FPGA. Many algorithms have been proposed to accelerate regular expression matching via mapping of a nondeterministic finite automaton into a circuit implemented in an FPGA. These algorithms exploit unique features of the FPGA to achieve high throughput. On the other hand the FPGA poses a limit on the number of regular expressions by its limited resources. In this paper, we investigate applicability of NFA reduction techniques - a formal aparatus to reduce the number of states and transitions in NFA prior to its mapping into FPGA. The paper presents several NFA reduction techniques, each with a different reduction power and time complexity. The evaluation utilizes regular expressions from Snort and L7 decoder. The best NFA reduction algorithms achieve more than 66% reduction in the number of states for a Snort ftp module. Such a reduction translates directly into 66% LUT and FF saving in the FPGA.
dcterms:title
NFA Reduction for Regular Expressions Matching Using FPGA NFA Reduction for Regular Expressions Matching Using FPGA
skos:prefLabel
NFA Reduction for Regular Expressions Matching Using FPGA NFA Reduction for Regular Expressions Matching Using FPGA
skos:notation
RIV/00216305:26230/13:PU107071!RIV14-MSM-26230___
n15:predkladatel
n19:orjk%3A26230
n3:aktivita
n5:Z n5:S n5:P
n3:aktivity
P(ED1.1.00/02.0070), S, Z(MSM0021630528)
n3:dodaniDat
n4:2014
n3:domaciTvurceVysledku
n7:3991385 n7:4198727 n7:9452591
n3:druhVysledku
n22:D
n3:duvernostUdaju
n8:S
n3:entitaPredkladatele
n11:predkladatel
n3:idSjednocenehoVysledku
91786
n3:idVysledku
RIV/00216305:26230/13:PU107071
n3:jazykVysledku
n18:eng
n3:klicovaSlova
FPGA, NFA, Reduction, Regular expressions matching
n3:klicoveSlovo
n12:Regular%20expressions%20matching n12:FPGA n12:NFA n12:Reduction
n3:kontrolniKodProRIV
[16775E5DBF8D]
n3:mistoKonaniAkce
Kyoto
n3:mistoVydani
Kyoto
n3:nazevZdroje
Proceedings of the 2013 International Conference on Field Programmable Technology
n3:obor
n21:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n16:ED1.1.00%2F02.0070
n3:rokUplatneniVysledku
n4:2013
n3:tvurceVysledku
Kořenek, Jan Žádník, Martin Košař, Vlastimil
n3:typAkce
n13:WRD
n3:zahajeniAkce
2013-12-09+01:00
n3:zamer
n17:MSM0021630528
s:numberOfPages
4
n14:hasPublisher
IEEE Computer Society
n20:isbn
978-1-4799-2199-7
n23:organizacniJednotka
26230