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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F13%3APU106378%21RIV14-MSM-26230___
rdf:type
skos:Concept n14:Vysledek
dcterms:description
The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used. The paper presents a methodology of fault tolerant system design into an FPGA with the ability of the transient fault and the permanent fault mitigation. The transient fault mitigation is done by the partial dynamic reconfiguration. The mitigation of a certain number of permanent faults is based on using a specific fault tolerant architecture occupiing less resources than the previosly used one and excluding the faulty part of the FPGA. This inovative technique is based on the precompiled configurations stored in an external memory. To reduce the required space for a partial bitstream the relocation technique is used.
dcterms:title
Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area
skos:prefLabel
Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area
skos:notation
RIV/00216305:26230/13:PU106378!RIV14-MSM-26230___
n14:predkladatel
n18:orjk%3A26230
n3:aktivita
n6:S n6:P n6:Z
n3:aktivity
P(ED1.1.00/02.0070), P(LD12036), S, Z(MSM0021630528)
n3:dodaniDat
n15:2014
n3:domaciTvurceVysledku
n4:1196332 n4:8608512 n4:7825668
n3:druhVysledku
n12:D
n3:duvernostUdaju
n20:S
n3:entitaPredkladatele
n8:predkladatel
n3:idSjednocenehoVysledku
87593
n3:idVysledku
RIV/00216305:26230/13:PU106378
n3:jazykVysledku
n10:eng
n3:klicovaSlova
methodology, partial dynamic reconfiguration, relocation, synchronization, limited redundant space
n3:klicoveSlovo
n13:synchronization n13:limited%20redundant%20space n13:partial%20dynamic%20reconfiguration n13:methodology n13:relocation
n3:kontrolniKodProRIV
[92FCF5507E69]
n3:mistoKonaniAkce
Santander
n3:mistoVydani
Santander
n3:nazevZdroje
16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
n3:obor
n17:IN
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n11:LD12036 n11:ED1.1.00%2F02.0070
n3:rokUplatneniVysledku
n15:2013
n3:tvurceVysledku
Straka, Martin Mičulka, Lukáš Kotásek, Zdeněk
n3:typAkce
n22:WRD
n3:zahajeniAkce
2013-09-04+02:00
n3:zamer
n21:MSM0021630528
s:numberOfPages
8
n7:hasPublisher
IEEE Computer Society
n16:isbn
978-0-7695-5074-9
n9:organizacniJednotka
26230