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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F13%3APU106326%21RIV14-MSM-26230___
rdf:type
skos:Concept n14:Vysledek
dcterms:description
With the growing speed of computer networks, core routers have to increase performance of longest prefix match (LPM) operation on IP addresses. While existing LPM algorithms are able to achieve high throughput for IPv4 addresses, the IPv6 processing speed is limited. To achieve 100 Gbps throughput, LPM operation has to be processed in dedicated hardware and a forwarding table has to fit into the on-chip memory. Current LPM algorithms need a large memory to store IPv6 forwarding tables or use compression with dynamic data structres, which can not be simply implemented in hardware. Therefore we provide analysis of available forwarding tables of core routers and propose a new representation of prefix sets. The proposed representation has very low memory demands and is suitable for high-speed pipelined processing, which is shown on new highly pipelined hardware architecture with 100 Gbps throughput. With the growing speed of computer networks, core routers have to increase performance of longest prefix match (LPM) operation on IP addresses. While existing LPM algorithms are able to achieve high throughput for IPv4 addresses, the IPv6 processing speed is limited. To achieve 100 Gbps throughput, LPM operation has to be processed in dedicated hardware and a forwarding table has to fit into the on-chip memory. Current LPM algorithms need a large memory to store IPv6 forwarding tables or use compression with dynamic data structres, which can not be simply implemented in hardware. Therefore we provide analysis of available forwarding tables of core routers and propose a new representation of prefix sets. The proposed representation has very low memory demands and is suitable for high-speed pipelined processing, which is shown on new highly pipelined hardware architecture with 100 Gbps throughput.
dcterms:title
Towards Hardware Architecture for Memory Efficient IPv4/IPv6 Lookup in 100 Gbps Networks Towards Hardware Architecture for Memory Efficient IPv4/IPv6 Lookup in 100 Gbps Networks
skos:prefLabel
Towards Hardware Architecture for Memory Efficient IPv4/IPv6 Lookup in 100 Gbps Networks Towards Hardware Architecture for Memory Efficient IPv4/IPv6 Lookup in 100 Gbps Networks
skos:notation
RIV/00216305:26230/13:PU106326!RIV14-MSM-26230___
n14:predkladatel
n15:orjk%3A26230
n3:aktivita
n11:S n11:P n11:Z
n3:aktivity
P(ED1.1.00/02.0070), S, Z(MSM0021630528)
n3:dodaniDat
n5:2014
n3:domaciTvurceVysledku
Skačan, Martin n16:9452591 n16:9461728
n3:druhVysledku
n4:D
n3:duvernostUdaju
n13:S
n3:entitaPredkladatele
n20:predkladatel
n3:idSjednocenehoVysledku
111378
n3:idVysledku
RIV/00216305:26230/13:PU106326
n3:jazykVysledku
n21:eng
n3:klicovaSlova
IP address, Longest Prefix Match, Memory
n3:klicoveSlovo
n9:IP%20address n9:Longest%20Prefix%20Match n9:Memory
n3:kontrolniKodProRIV
[FB45ECBFC05D]
n3:mistoKonaniAkce
Karlovy Vary
n3:mistoVydani
Brno
n3:nazevZdroje
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
n3:obor
n10:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n17:ED1.1.00%2F02.0070
n3:rokUplatneniVysledku
n5:2013
n3:tvurceVysledku
Skačan, Martin Kořenek, Jan Matoušek, Jiří
n3:typAkce
n22:WRD
n3:zahajeniAkce
2013-04-08+02:00
n3:zamer
n19:MSM0021630528
s:numberOfPages
4
n18:hasPublisher
IEEE Computer Society
n7:isbn
978-1-4673-6133-0
n23:organizacniJednotka
26230