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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F13%3APU106307%21RIV14-MSM-26230___
rdf:type
n17:Vysledek skos:Concept
dcterms:description
As the speed of current computer networks in- creases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow. As the speed of current computer networks in- creases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow.
dcterms:title
Hardware Architecture for the Fast Pattern Matching Hardware Architecture for the Fast Pattern Matching
skos:prefLabel
Hardware Architecture for the Fast Pattern Matching Hardware Architecture for the Fast Pattern Matching
skos:notation
RIV/00216305:26230/13:PU106307!RIV14-MSM-26230___
n17:predkladatel
n18:orjk%3A26230
n3:aktivita
n4:S n4:Z
n3:aktivity
S, Z(MSM0021630528)
n3:dodaniDat
n11:2014
n3:domaciTvurceVysledku
n8:9452591 n8:3991385 n8:8564892
n3:druhVysledku
n20:D
n3:duvernostUdaju
n9:S
n3:entitaPredkladatele
n12:predkladatel
n3:idSjednocenehoVysledku
77056
n3:idVysledku
RIV/00216305:26230/13:PU106307
n3:jazykVysledku
n21:eng
n3:klicovaSlova
pattern matching, intrussion detection system, regular expression, FPGA
n3:klicoveSlovo
n5:pattern%20matching n5:FPGA n5:regular%20expression n5:intrussion%20detection%20system
n3:kontrolniKodProRIV
[CCFBDE4DC23D]
n3:mistoKonaniAkce
Karlovy Vary
n3:mistoVydani
Brno
n3:nazevZdroje
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
n3:obor
n6:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:rokUplatneniVysledku
n11:2013
n3:tvurceVysledku
Kaštil, Jan Kořenek, Jan Košař, Vlastimil
n3:typAkce
n16:WRD
n3:zahajeniAkce
2013-04-08+02:00
n3:zamer
n13:MSM0021630528
s:numberOfPages
4
n15:hasPublisher
IEEE Computer Society
n22:isbn
978-1-4673-6133-0
n7:organizacniJednotka
26230