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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F13%3APU106283%21RIV14-GA0-26230___
rdf:type
skos:Concept n15:Vysledek
dcterms:description
This paper presents an evolvable hardware system, fully contained in an FPGA, which is capable of autonomously generating digital processing circuits, implemented on an array of processing elements (PEs). Candidate circuits are generated by an embedded evolutionary algorithm and implemented by means of dynamic partial reconfiguration, enabling evaluation in the final hardware. The PE array follows a systolic approach, and PEs do not contain extra logic such as path multiplexers or unused logic, so array performance is high. Hardware evaluation in the target device and the fast reconfiguration engine used yield smaller reconfiguration than evaluation times. This means that the complete evaluation cycle is faster than software-based approaches and previous evolvable digital systems. The selected application is digital image filtering and edge detection. The evolved filters yield better quality than classic linear and nonlinear filters using mean absolute error as standard comparison metric. This paper presents an evolvable hardware system, fully contained in an FPGA, which is capable of autonomously generating digital processing circuits, implemented on an array of processing elements (PEs). Candidate circuits are generated by an embedded evolutionary algorithm and implemented by means of dynamic partial reconfiguration, enabling evaluation in the final hardware. The PE array follows a systolic approach, and PEs do not contain extra logic such as path multiplexers or unused logic, so array performance is high. Hardware evaluation in the target device and the fast reconfiguration engine used yield smaller reconfiguration than evaluation times. This means that the complete evaluation cycle is faster than software-based approaches and previous evolvable digital systems. The selected application is digital image filtering and edge detection. The evolved filters yield better quality than classic linear and nonlinear filters using mean absolute error as standard comparison metric.
dcterms:title
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing
skos:prefLabel
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing
skos:notation
RIV/00216305:26230/13:PU106283!RIV14-GA0-26230___
n15:predkladatel
n16:orjk%3A26230
n3:aktivita
n6:P
n3:aktivity
P(ED1.1.00/02.0070), P(GAP103/10/1517)
n3:cisloPeriodika
8
n3:dodaniDat
n14:2014
n3:domaciTvurceVysledku
n12:7173873
n3:druhVysledku
n7:J
n3:duvernostUdaju
n19:S
n3:entitaPredkladatele
n18:predkladatel
n3:idSjednocenehoVysledku
104561
n3:idVysledku
RIV/00216305:26230/13:PU106283
n3:jazykVysledku
n9:eng
n3:klicovaSlova
evolutionary computing, genetic algorithms, evolvable hardware, FPGAs, self-adaptive systems, reconfigurable hardware, adaptable architectures, autonomous systems
n3:klicoveSlovo
n4:autonomous%20systems n4:evolutionary%20computing n4:evolvable%20hardware n4:adaptable%20architectures n4:reconfigurable%20hardware n4:genetic%20algorithms n4:self-adaptive%20systems n4:FPGAs
n3:kodStatuVydavatele
US - Spojené státy americké
n3:kontrolniKodProRIV
[E723D39221C4]
n3:nazevZdroje
IEEE TRANSACTIONS ON COMPUTERS
n3:obor
n13:JC
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
6
n3:projekt
n17:ED1.1.00%2F02.0070 n17:GAP103%2F10%2F1517
n3:rokUplatneniVysledku
n14:2013
n3:svazekPeriodika
62
n3:tvurceVysledku
Otero, Andres Salvador, Ruben Mora, Javier De la Torre, Eduardo Sekanina, Lukáš Riesgo, Teresa
n3:wos
000321221000002
s:issn
0018-9340
s:numberOfPages
12
n11:doi
10.1109/TC.2013.78
n20:organizacniJednotka
26230