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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F12%3APU101888%21RIV13-MSM-26230___
rdf:type
skos:Concept n14:Vysledek
dcterms:description
Packet parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very large chip area. We propose novel architecture of pipelined packet parser, which in addition to high throughput (over 100 Gb/s) offers also low latency. Moreover, the latency to throughput ratio can be finely tuned to fit the particular application. The parser is handoptimized thanks to the direct implementation in VHDL, yet the structure is very uniform and easily extensible for new protocols. Packet parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very large chip area. We propose novel architecture of pipelined packet parser, which in addition to high throughput (over 100 Gb/s) offers also low latency. Moreover, the latency to throughput ratio can be finely tuned to fit the particular application. The parser is handoptimized thanks to the direct implementation in VHDL, yet the structure is very uniform and easily extensible for new protocols.
dcterms:title
Low-Latency Modular Packet Header Parser for FPGA Low-Latency Modular Packet Header Parser for FPGA
skos:prefLabel
Low-Latency Modular Packet Header Parser for FPGA Low-Latency Modular Packet Header Parser for FPGA
skos:notation
RIV/00216305:26230/12:PU101888!RIV13-MSM-26230___
n14:predkladatel
n19:orjk%3A26230
n3:aktivita
n5:S n5:P n5:Z
n3:aktivity
P(ED1.1.00/02.0070), P(LM2010005), S, Z(MSM0021630528)
n3:dodaniDat
n23:2013
n3:domaciTvurceVysledku
n9:9452591 Kekely, Lukáš
n3:druhVysledku
n22:D
n3:duvernostUdaju
n12:S
n3:entitaPredkladatele
n20:predkladatel
n3:idSjednocenehoVysledku
147527
n3:idVysledku
RIV/00216305:26230/12:PU101888
n3:jazykVysledku
n18:eng
n3:klicovaSlova
Packet Parsing, Latency, FPGA
n3:klicoveSlovo
n6:FPGA n6:Packet%20Parsing n6:Latency
n3:kontrolniKodProRIV
[F05397F0DACB]
n3:mistoKonaniAkce
Austin, TX
n3:mistoVydani
Austin
n3:nazevZdroje
ACM/IEEE Symposium on Architectures for Networking and Communications Systems
n3:obor
n10:IN
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
3
n3:projekt
n15:ED1.1.00%2F02.0070 n15:LM2010005
n3:rokUplatneniVysledku
n23:2012
n3:tvurceVysledku
Kekely, Lukáš Kořenek, Jan Puš, Viktor
n3:typAkce
n16:WRD
n3:zahajeniAkce
2012-10-29+01:00
n3:zamer
n21:MSM0021630528
s:numberOfPages
2
n8:hasPublisher
Association for Computing Machinery
n4:isbn
978-1-4503-1685-9
n13:organizacniJednotka
26230