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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F12%3APU101876%21RIV13-MSM-26230___
rdf:type
n11:Vysledek skos:Concept
dcterms:description
Many packet classification algorithms were proposed to deal with the rapidly growing speed of computer networks. Unfortunately all of these algorithms are able to achieve high throughput only at the cost of excessively large memory and can be used only for small sets of rules. We propose new algorithm that uses four techniques to lower the memory requirements: division of rule set into subsets, removal of critical rules, prefix coloring and perfect hashing. The algorithm is designed for pipelined hardware implementation, can achieve the throughput of 266 million packets per second, which corresponds to 178 Gb/s for the shortest 64B packets, and outperforms older approaches in terms of memory requirements by 66 % in average for the rule sets available to us. Many packet classification algorithms were proposed to deal with the rapidly growing speed of computer networks. Unfortunately all of these algorithms are able to achieve high throughput only at the cost of excessively large memory and can be used only for small sets of rules. We propose new algorithm that uses four techniques to lower the memory requirements: division of rule set into subsets, removal of critical rules, prefix coloring and perfect hashing. The algorithm is designed for pipelined hardware implementation, can achieve the throughput of 266 million packets per second, which corresponds to 178 Gb/s for the shortest 64B packets, and outperforms older approaches in terms of memory requirements by 66 % in average for the rule sets available to us.
dcterms:title
Reducing memory in high-speed packet classification Reducing memory in high-speed packet classification
skos:prefLabel
Reducing memory in high-speed packet classification Reducing memory in high-speed packet classification
skos:notation
RIV/00216305:26230/12:PU101876!RIV13-MSM-26230___
n11:predkladatel
n23:orjk%3A26230
n3:aktivita
n14:S n14:P n14:Z
n3:aktivity
P(ED1.1.00/02.0070), S, Z(MSM0021630528)
n3:dodaniDat
n10:2013
n3:domaciTvurceVysledku
n20:6647596 n20:9452591
n3:druhVysledku
n9:D
n3:duvernostUdaju
n18:S
n3:entitaPredkladatele
n22:predkladatel
n3:idSjednocenehoVysledku
164484
n3:idVysledku
RIV/00216305:26230/12:PU101876
n3:jazykVysledku
n4:eng
n3:klicovaSlova
FPGA, SRAM, hardware, parallelism, classification
n3:klicoveSlovo
n5:parallelism n5:hardware n5:SRAM n5:FPGA n5:classification
n3:kontrolniKodProRIV
[176205BDF910]
n3:mistoKonaniAkce
Cyprus
n3:mistoVydani
Limassol
n3:nazevZdroje
Proceedings of the 8th International Wireless Communications and Mobile Computing Conference
n3:obor
n19:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n17:ED1.1.00%2F02.0070
n3:rokUplatneniVysledku
n10:2012
n3:tvurceVysledku
Kořenek, Jan Puš, Viktor
n3:typAkce
n15:WRD
n3:zahajeniAkce
2012-08-27+02:00
n3:zamer
n12:MSM0021630528
s:numberOfPages
6
n16:hasPublisher
Frederick University
n13:isbn
978-1-4577-1377-4
n6:organizacniJednotka
26230