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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F12%3APU101849%21RIV13-MSM-26230___
rdf:type
n12:Vysledek skos:Concept
rdfs:seeAlso
http://dl.acm.org/citation.cfm?id=2396573
dcterms:description
NetFPGA-1G has shown its potential in enabling fast traffic processing while introducing no packet loss and minimal delay. Now it is time to scale down in order to enable a massive deployment of the FPGA solutions in networking. We propose and build a low-cost and low-power platform which is be capable of hosting embedded applications with FPGA support. Such a platform might enable faster deployment of new ideas in networking and might prove useful for large-scale experiments (stacks of platforms) as its size, power consumption and cost are expected to be ten times lower of the NetFPGA-cube. It is recognized that the FPGA coupled with the host processor comprises a powerful platform for network traffic processing. The logic of such a solution is clear. Computational intensive tasks are handled by the FPGA logic whereas more complex tasks by the processor. The proposed platform aims at such a design in which the FPGA and the processor are even more tightly coupled together on a single die S NetFPGA-1G has shown its potential in enabling fast traffic processing while introducing no packet loss and minimal delay. Now it is time to scale down in order to enable a massive deployment of the FPGA solutions in networking. We propose and build a low-cost and low-power platform which is be capable of hosting embedded applications with FPGA support. Such a platform might enable faster deployment of new ideas in networking and might prove useful for large-scale experiments (stacks of platforms) as its size, power consumption and cost are expected to be ten times lower of the NetFPGA-cube. It is recognized that the FPGA coupled with the host processor comprises a powerful platform for network traffic processing. The logic of such a solution is clear. Computational intensive tasks are handled by the FPGA logic whereas more complex tasks by the processor. The proposed platform aims at such a design in which the FPGA and the processor are even more tightly coupled together on a single die S
dcterms:title
A New Embedded Platform for Rapid Development of Networking Applications A New Embedded Platform for Rapid Development of Networking Applications
skos:prefLabel
A New Embedded Platform for Rapid Development of Networking Applications A New Embedded Platform for Rapid Development of Networking Applications
skos:notation
RIV/00216305:26230/12:PU101849!RIV13-MSM-26230___
n12:predkladatel
n19:orjk%3A26230
n5:aktivita
n8:Z n8:S n8:P
n5:aktivity
P(ED1.1.00/02.0070), P(VG20102015022), S, Z(MSM0021630528)
n5:dodaniDat
n14:2013
n5:domaciTvurceVysledku
Korček, Pavol n13:1105000 n13:9452591 n13:3991385 n13:4198727
n5:druhVysledku
n16:D
n5:duvernostUdaju
n24:S
n5:entitaPredkladatele
n21:predkladatel
n5:idSjednocenehoVysledku
120361
n5:idVysledku
RIV/00216305:26230/12:PU101849
n5:jazykVysledku
n17:eng
n5:klicovaSlova
FPGA, Zynq, Embedded, Networking
n5:klicoveSlovo
n9:Networking n9:FPGA n9:Embedded n9:Zynq
n5:kontrolniKodProRIV
[404AC37C22FC]
n5:mistoKonaniAkce
Austin, TX
n5:mistoVydani
Austin
n5:nazevZdroje
Proceedings of the 2012 Seventh ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2012)
n5:obor
n6:IN
n5:pocetDomacichTvurcuVysledku
5
n5:pocetTvurcuVysledku
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n5:projekt
n15:ED1.1.00%2F02.0070 n15:VG20102015022
n5:rokUplatneniVysledku
n14:2012
n5:tvurceVysledku
Viktorin, Jan Košař, Vlastimil Korček, Pavol Kořenek, Jan Žádník, Martin
n5:typAkce
n10:WRD
n5:zahajeniAkce
2012-10-29+01:00
n5:zamer
n22:MSM0021630528
s:numberOfPages
2
n25:doi
10.1145/2396556.2396573
n7:hasPublisher
IEEE Computer Society
n20:isbn
978-1-4503-1684-2
n23:organizacniJednotka
26230