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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F11%3APU96100%21RIV12-MSM-26230___
rdf:type
n8:Vysledek skos:Concept
dcterms:description
The contribution presents an architecture for embedded video and signal processing system. The architecture is based on embedded microcomputer with ARM-based CPU and FPGA on the AX32 platform. While the CPU is necessary and integral part of the system, the signal and video processing tasks are %22offloaded%22 to the FPGA in order to save computational power and energy. The target application is in standalone traffic monitoring systems with or without video processing and embedded sensory systems, e.g. in robots. Power consumption is critical as the applications are intended with battery power and also because in some applications, hermetic packaging not allowing heating through e.g. flow of air must be used. The contribution presents a concept of the system, the video and signal processing approach, and draws some conclusions. The contribution presents an architecture for embedded video and signal processing system. The architecture is based on embedded microcomputer with ARM-based CPU and FPGA on the AX32 platform. While the CPU is necessary and integral part of the system, the signal and video processing tasks are %22offloaded%22 to the FPGA in order to save computational power and energy. The target application is in standalone traffic monitoring systems with or without video processing and embedded sensory systems, e.g. in robots. Power consumption is critical as the applications are intended with battery power and also because in some applications, hermetic packaging not allowing heating through e.g. flow of air must be used. The contribution presents a concept of the system, the video and signal processing approach, and draws some conclusions.
dcterms:title
AX32 Low Power Embedded Video Enabled System Using FPGA AX32 Low Power Embedded Video Enabled System Using FPGA
skos:prefLabel
AX32 Low Power Embedded Video Enabled System Using FPGA AX32 Low Power Embedded Video Enabled System Using FPGA
skos:notation
RIV/00216305:26230/11:PU96100!RIV12-MSM-26230___
n8:predkladatel
n9:orjk%3A26230
n4:aktivita
n7:S n7:P n7:Z
n4:aktivity
P(7H10011), P(7H10013), S, Z(MSM0021630528)
n4:dodaniDat
n14:2012
n4:domaciTvurceVysledku
Korček, Pavol n11:6518125 n11:3991288 n11:3353443 n11:9340386 n11:3442411
n4:druhVysledku
n22:D
n4:duvernostUdaju
n16:S
n4:entitaPredkladatele
n15:predkladatel
n4:idSjednocenehoVysledku
187705
n4:idVysledku
RIV/00216305:26230/11:PU96100
n4:jazykVysledku
n23:eng
n4:klicovaSlova
AX32 platform, embedded system, low power, video/image processing, radar signal processing
n4:klicoveSlovo
n12:radar%20signal%20processing n12:AX32%20platform n12:low%20power n12:embedded%20system n12:video%2Fimage%20processing
n4:kontrolniKodProRIV
[53E350E0610F]
n4:mistoKonaniAkce
Chania
n4:mistoVydani
Chania
n4:nazevZdroje
Proceedings of the 21th Conference on Field Programmable Logic and Applications Workshop
n4:obor
n13:IN
n4:pocetDomacichTvurcuVysledku
6
n4:pocetTvurcuVysledku
6
n4:projekt
n5:7H10013 n5:7H10011
n4:rokUplatneniVysledku
n14:2011
n4:tvurceVysledku
Zemčík, Pavel Šustek, Jiří Široký, Vít Maršík, Lukáš Fučík, Otto Korček, Pavol
n4:typAkce
n19:WRD
n4:zahajeniAkce
2011-09-05+02:00
n4:zamer
n18:MSM0021630528
s:numberOfPages
2
n21:hasPublisher
Institute of Electrical and Electronics Engineers
n10:isbn
978-0-7695-4529-5
n20:organizacniJednotka
26230