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Namespace Prefixes

PrefixIRI
n21http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n14http://purl.org/net/nknouf/ns/bibtex#
n13http://localhost/temp/predkladatel/
n18http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n17http://linked.opendata.cz/resource/domain/vavai/projekt/
n11http://linked.opendata.cz/resource/domain/vavai/subjekt/
n10http://linked.opendata.cz/ontology/domain/vavai/
n22http://linked.opendata.cz/resource/domain/vavai/zamer/
n19https://schema.org/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n5http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F00216305%3A26230%2F11%3APU96032%21RIV13-MSM-26230___/
n6http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n9http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n15http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n4http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n23http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n20http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n16http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F11%3APU96032%21RIV13-MSM-26230___
rdf:type
n10:Vysledek skos:Concept
dcterms:description
In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAG interface and subsequent  dynamic reconfiguration of  FPGA.  It allows to select region of the FPGA for  SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology. In the paper, the SEU simulation framework for testing fault tolerant system designs implemented into FPGA is presented. The framework is based on SEU generation outside FPGA (in personal computer) and the transport of modified bitstream through the JTAG interface and subsequent  dynamic reconfiguration of  FPGA.  It allows to select region of the FPGA for  SEU placing. The SEU simulator does not require any changes in the tested design and is fully independent on the function implemented into FPGA. The requirements on the SEU generator and its properties are described in the paper as well. The external SEU generator for Xilinx FPGA was implemented and verified on evaluation board ML506 with Vitrex5 for different types of RTL circuits and fault tolerant architectures. The experimatal results demonstrated the effectiveness of the methodology.
dcterms:title
SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems
skos:prefLabel
SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems
skos:notation
RIV/00216305:26230/11:PU96032!RIV13-MSM-26230___
n10:predkladatel
n11:orjk%3A26230
n3:aktivita
n15:Z n15:S n15:P
n3:aktivity
P(GA102/09/1668), S, Z(MSM0021630528)
n3:dodaniDat
n16:2013
n3:domaciTvurceVysledku
n18:7825668 n18:8564892 n18:1196332
n3:druhVysledku
n23:D
n3:duvernostUdaju
n9:S
n3:entitaPredkladatele
n5:predkladatel
n3:idSjednocenehoVysledku
229030
n3:idVysledku
RIV/00216305:26230/11:PU96032
n3:jazykVysledku
n4:eng
n3:klicovaSlova
SEU, simulatotion, generator, framework, online testing, fault tolerance
n3:klicoveSlovo
n6:generator n6:SEU n6:online%20testing n6:fault%20tolerance n6:simulatotion n6:framework
n3:kontrolniKodProRIV
[E17B8A69CFAA]
n3:mistoKonaniAkce
Oulu
n3:mistoVydani
Oulu
n3:nazevZdroje
14th EUROMICRO Conference on Digital System Design
n3:obor
n20:IN
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n17:GA102%2F09%2F1668
n3:rokUplatneniVysledku
n16:2011
n3:tvurceVysledku
Kotásek, Zdeněk Straka, Martin Kaštil, Jan
n3:typAkce
n21:WRD
n3:zahajeniAkce
2011-08-31+02:00
n3:zamer
n22:MSM0021630528
s:numberOfPages
8
n14:hasPublisher
IEEE Computer Society
n19:isbn
978-0-7695-4494-6
n13:organizacniJednotka
26230