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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F11%3APU96017%21RIV12-MSM-26230___
rdf:type
n8:Vysledek skos:Concept
dcterms:description
Packet classification is a widely used operation in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays algorithms implemented in hardware can achieve multigigabit speeds, but suffer with great memory overhead. We propose a new algorithm and hardware architecture which reduces memory requirements of decomposition based methods for packet classification. The algorithm uses prefix coloring to reduce large amount of Cartesian product rules at the cost of an additional pipelined processing and a few bits added into results of the longest prefix match operation. The proposed hardware architecture is designed as a processing pipeline with the throughput of 266 million packets per second using commodity FPGA and one external memory. The greatest strength of the algorithm is the constant time complexity of the search operation, which makes the solution resistant to various classes of netw Packet classification is a widely used operation in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays algorithms implemented in hardware can achieve multigigabit speeds, but suffer with great memory overhead. We propose a new algorithm and hardware architecture which reduces memory requirements of decomposition based methods for packet classification. The algorithm uses prefix coloring to reduce large amount of Cartesian product rules at the cost of an additional pipelined processing and a few bits added into results of the longest prefix match operation. The proposed hardware architecture is designed as a processing pipeline with the throughput of 266 million packets per second using commodity FPGA and one external memory. The greatest strength of the algorithm is the constant time complexity of the search operation, which makes the solution resistant to various classes of netw
dcterms:title
Hardware Architecture for Packet Classification with Prefix Coloring Hardware Architecture for Packet Classification with Prefix Coloring
skos:prefLabel
Hardware Architecture for Packet Classification with Prefix Coloring Hardware Architecture for Packet Classification with Prefix Coloring
skos:notation
RIV/00216305:26230/11:PU96017!RIV12-MSM-26230___
n8:predkladatel
n18:orjk%3A26230
n3:aktivita
n9:Z
n3:aktivity
Z(MSM0021630528)
n3:dodaniDat
n12:2012
n3:domaciTvurceVysledku
n4:6647596 Kajan, Michal n4:9452591
n3:druhVysledku
n17:D
n3:duvernostUdaju
n5:S
n3:entitaPredkladatele
n14:predkladatel
n3:idSjednocenehoVysledku
201732
n3:idVysledku
RIV/00216305:26230/11:PU96017
n3:jazykVysledku
n13:eng
n3:klicovaSlova
FPGA, SRAM, hardware, parallelism, classification
n3:klicoveSlovo
n10:SRAM n10:FPGA n10:hardware n10:classification n10:parallelism
n3:kontrolniKodProRIV
[5D84BCAF56C0]
n3:mistoKonaniAkce
Cottbus
n3:mistoVydani
Cottbus
n3:nazevZdroje
IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
n3:obor
n11:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:rokUplatneniVysledku
n12:2011
n3:tvurceVysledku
Kořenek, Jan Puš, Viktor Kajan, Michal
n3:typAkce
n22:WRD
n3:zahajeniAkce
2011-04-13+02:00
n3:zamer
n19:MSM0021630528
s:numberOfPages
6
n15:hasPublisher
IEEE Computer Society
n6:isbn
978-1-4244-9753-9
n16:organizacniJednotka
26230