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Namespace Prefixes

PrefixIRI
dctermshttp://purl.org/dc/terms/
n17http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F00216305%3A26230%2F11%3APU95993%21RIV13-MSM-26230___/
n5http://localhost/temp/predkladatel/
n12http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n6http://linked.opendata.cz/resource/domain/vavai/projekt/
n11http://linked.opendata.cz/resource/domain/vavai/subjekt/
n10http://linked.opendata.cz/ontology/domain/vavai/
n22http://linked.opendata.cz/resource/domain/vavai/zamer/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
rdfshttp://www.w3.org/2000/01/rdf-schema#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n15http://bibframe.org/vocab/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n14http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n9http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n21http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n16http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n18http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n8http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n4http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F11%3APU95993%21RIV13-MSM-26230___
rdf:type
skos:Concept n10:Vysledek
rdfs:seeAlso
http://drops.dagstuhl.de/opus/volltexte/2011/3060/
dcterms:description
Application-specific instruction set processors are the core of nowadays embedded systems. Therefore, the designers need to have powerful tools for the processor design. The tools should be generated automatically based on a processor description. One of the most important tools is the simulator. It is used during a testing phase of the processor design and during target software development. The key feature of the simulator is its speed. The concept of a special simulation type - translated simulation - is presented in this paper. This simulation exploits information from a target C compiler. Both the simulator and the C compiler are generated based on the processor description in an architecture description language ISAC. Experimental results of this concept show very good simulation speed and fast generation of the simulator. Application-specific instruction set processors are the core of nowadays embedded systems. Therefore, the designers need to have powerful tools for the processor design. The tools should be generated automatically based on a processor description. One of the most important tools is the simulator. It is used during a testing phase of the processor design and during target software development. The key feature of the simulator is its speed. The concept of a special simulation type - translated simulation - is presented in this paper. This simulation exploits information from a target C compiler. Both the simulator and the C compiler are generated based on the processor description in an architecture description language ISAC. Experimental results of this concept show very good simulation speed and fast generation of the simulator.
dcterms:title
Fast Translated Simulation of ASIPs Fast Translated Simulation of ASIPs
skos:prefLabel
Fast Translated Simulation of ASIPs Fast Translated Simulation of ASIPs
skos:notation
RIV/00216305:26230/11:PU95993!RIV13-MSM-26230___
n10:predkladatel
n11:orjk%3A26230
n3:aktivita
n16:Z n16:S n16:P
n3:aktivity
P(7H10014), P(FR-TI1/038), P(GD102/09/H042), S, Z(MSM0021630528)
n3:cisloPeriodika
1
n3:dodaniDat
n4:2013
n3:domaciTvurceVysledku
n12:1114840 n12:2811707 n12:3398706 n12:9238948
n3:druhVysledku
n18:J
n3:duvernostUdaju
n9:S
n3:entitaPredkladatele
n17:predkladatel
n3:idSjednocenehoVysledku
199377
n3:idVysledku
RIV/00216305:26230/11:PU95993
n3:jazykVysledku
n21:eng
n3:klicovaSlova
Hardware/sofware co-design, Translated simulation, Architecture description language, Application-specific instruction set processors
n3:klicoveSlovo
n14:Hardware%2Fsofware%20co-design n14:Translated%20simulation n14:Application-specific%20instruction%20set%20processors n14:Architecture%20description%20language
n3:kodStatuVydavatele
DE - Spolková republika Německo
n3:kontrolniKodProRIV
[AE7310634552]
n3:nazevZdroje
OpenAccess Series in Informatics (OASIcs)
n3:obor
n8:JC
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
4
n3:projekt
n6:FR-TI1%2F038 n6:GD102%2F09%2FH042 n6:7H10014
n3:rokUplatneniVysledku
n4:2011
n3:svazekPeriodika
16
n3:tvurceVysledku
Přikryl, Zdeněk Kolář, Dušan Křoustek, Jakub Hruška, Tomáš
n3:zamer
n22:MSM0021630528
s:issn
2190-6807
s:numberOfPages
8
n15:doi
10.4230/OASIcs.MEMICS.2010.93
n5:organizacniJednotka
26230