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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F10%3APU90534%21RIV11-GA0-26230___
rdf:type
skos:Concept n18:Vysledek
dcterms:description
A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was developed to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark problem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution. A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was developed to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark problem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution.
dcterms:title
Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units
skos:prefLabel
Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units
skos:notation
RIV/00216305:26230/10:PU90534!RIV11-GA0-26230___
n3:aktivita
n7:Z n7:S n7:P
n3:aktivity
P(GA102/07/0850), P(GD102/09/H042), S, Z(MSM0021630528)
n3:cisloPeriodika
6
n3:dodaniDat
n19:2011
n3:domaciTvurceVysledku
n8:7173873 n8:6455719
n3:druhVysledku
n12:J
n3:duvernostUdaju
n5:S
n3:entitaPredkladatele
n11:predkladatel
n3:idSjednocenehoVysledku
261209
n3:idVysledku
RIV/00216305:26230/10:PU90534
n3:jazykVysledku
n17:eng
n3:klicovaSlova
<p align=left>Cartesian genetic programming, hardware accelerator, evolutionary circuit design, FPGA
n3:klicoveSlovo
n6:evolutionary%20circuit%20design n6:hardware%20accelerator n6:%3Cp%20align%3Dleft%3ECartesian%20genetic%20programming n6:FPGA
n3:kodStatuVydavatele
SK - Slovenská republika
n3:kontrolniKodProRIV
[82BE252EB837]
n3:nazevZdroje
Computing and Informatics
n3:obor
n15:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n9:GD102%2F09%2FH042 n9:GA102%2F07%2F0850
n3:rokUplatneniVysledku
n19:2010
n3:svazekPeriodika
29
n3:tvurceVysledku
Sekanina, Lukáš Vašíček, Zdeněk
n3:zamer
n13:MSM0021630528
s:issn
1335-9150
s:numberOfPages
13
n14:organizacniJednotka
26230