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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F10%3APU89650%21RIV12-MSM-26230___
rdf:type
skos:Concept n19:Vysledek
dcterms:description
Application-specific instruction set processors are the core of nowadays embedded systems. Therefore, the designers need to have powerful tools for the processor design. The tools should be generated automatically based on a processor description. One of the most important tools is the simulator. It is used during a testing phase of the processor design and during target software development. The key feature of the simulator is its speed. The concept of a special simulation type - translated simulation - is presented in this paper. This simulation exploits information from a target C compiler. Both the simulator and the C compiler are generated based on the processor description in an architecture description language ISAC. Experimental results of this concept show very good simulation speed and fast generation of the simulator. Application-specific instruction set processors are the core of nowadays embedded systems. Therefore, the designers need to have powerful tools for the processor design. The tools should be generated automatically based on a processor description. One of the most important tools is the simulator. It is used during a testing phase of the processor design and during target software development. The key feature of the simulator is its speed. The concept of a special simulation type - translated simulation - is presented in this paper. This simulation exploits information from a target C compiler. Both the simulator and the C compiler are generated based on the processor description in an architecture description language ISAC. Experimental results of this concept show very good simulation speed and fast generation of the simulator.
dcterms:title
Fast Translated Simulation of ASIPs Fast Translated Simulation of ASIPs
skos:prefLabel
Fast Translated Simulation of ASIPs Fast Translated Simulation of ASIPs
skos:notation
RIV/00216305:26230/10:PU89650!RIV12-MSM-26230___
n4:aktivita
n17:P n17:Z
n4:aktivity
P(7H10014), P(FR-TI1/038), P(GD102/09/H042), Z(MSM0021630503), Z(MSM0021630528)
n4:dodaniDat
n15:2012
n4:domaciTvurceVysledku
n11:1114840 n11:9238948 n11:3398706 n11:2811707
n4:druhVysledku
n9:D
n4:duvernostUdaju
n20:S
n4:entitaPredkladatele
n16:predkladatel
n4:idSjednocenehoVysledku
258840
n4:idVysledku
RIV/00216305:26230/10:PU89650
n4:jazykVysledku
n8:eng
n4:klicovaSlova
Hardware/sofware co-design, Translated simulation, Architecture description language, Application-specific instruction set processors
n4:klicoveSlovo
n18:Architecture%20description%20language n18:Translated%20simulation n18:Application-specific%20instruction%20set%20processors n18:Hardware%2Fsofware%20co-design
n4:kontrolniKodProRIV
[75DA3A3CE50C]
n4:mistoKonaniAkce
Mikulov
n4:mistoVydani
Brno
n4:nazevZdroje
6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
n4:obor
n6:IN
n4:pocetDomacichTvurcuVysledku
4
n4:pocetTvurcuVysledku
4
n4:projekt
n5:7H10014 n5:GD102%2F09%2FH042 n5:FR-TI1%2F038
n4:rokUplatneniVysledku
n15:2010
n4:tvurceVysledku
Hruška, Tomáš Křoustek, Jakub Přikryl, Zdeněk Kolář, Dušan
n4:typAkce
n14:WRD
n4:zahajeniAkce
2010-10-22+02:00
n4:zamer
n10:MSM0021630528 n10:MSM0021630503
s:numberOfPages
8
n3:hasPublisher
Masaryk University
n22:isbn
978-80-87342-10-7
n13:organizacniJednotka
26230