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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F10%3APU89630%21RIV11-GA0-26230___
rdf:type
skos:Concept n22:Vysledek
dcterms:description
In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented. In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller implemented inside FPGA is presented. The basic architecture and usage of the controller in the FPGA-based fault tolerant structure are described. The implementation of controller as fault tolerant component is described as well. The basic features and synthesis results of controller for Xilinx FPGA and comparison with MicroBlaze solution are presented.
dcterms:title
Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA
skos:prefLabel
Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA
skos:notation
RIV/00216305:26230/10:PU89630!RIV11-GA0-26230___
n3:aktivita
n5:Z n5:S n5:P
n3:aktivity
P(GA102/09/1668), P(GD102/09/H042), S, Z(MSM0021630528)
n3:dodaniDat
n18:2011
n3:domaciTvurceVysledku
n6:8564892 n6:1196332 n6:7825668
n3:druhVysledku
n14:D
n3:duvernostUdaju
n4:S
n3:entitaPredkladatele
n12:predkladatel
n3:idSjednocenehoVysledku
260383
n3:idVysledku
RIV/00216305:26230/10:PU89630
n3:jazykVysledku
n17:eng
n3:klicovaSlova
FPGA, partial reconfiguration, controller, fault tolerant system, architecture
n3:klicoveSlovo
n9:FPGA n9:architecture n9:controller n9:partial%20reconfiguration n9:fault%20tolerant%20system
n3:kontrolniKodProRIV
[AB06607CEA30]
n3:mistoKonaniAkce
Tampere
n3:mistoVydani
Tampere
n3:nazevZdroje
NORCHIP 2010
n3:obor
n15:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n13:GA102%2F09%2F1668 n13:GD102%2F09%2FH042
n3:rokUplatneniVysledku
n18:2010
n3:tvurceVysledku
Kaštil, Jan Kotásek, Zdeněk Straka, Martin
n3:typAkce
n19:WRD
n3:zahajeniAkce
2010-11-15+01:00
n3:zamer
n20:MSM0021630528
s:numberOfPages
4
n16:hasPublisher
IEEE Computer Society
n10:isbn
978-1-4244-8971-8
n21:organizacniJednotka
26230