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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F10%3APU89530%21RIV11-GA0-26230___
rdf:type
n6:Vysledek skos:Concept
dcterms:description
<p align=left>In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components. <p align=left>In this paper, activities which aim at developing a methodology of fault tolerant systems design into SRAM-based FPGA platforms with different types of diagnostic approaches are presented. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance of the digital design in FPGA. A generic controller for driving dynamic reconfiguration process of faulty unit is demonstrated and analyzed. Parameters of the generic partial reconfiguration controller are experimentally verified. The developed controller is compared with other approaches based on micro-controllers inside FPGA. A structure which can be used in fault tolerant system design into SRAM-based FPGA using partial reconfiguration controller is then described. The presented structure is proven fully functional on the ML506 development board for different types of RTL components.
dcterms:title
Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration
skos:prefLabel
Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration
skos:notation
RIV/00216305:26230/10:PU89530!RIV11-GA0-26230___
n3:aktivita
n5:Z n5:S n5:P
n3:aktivity
P(GA102/09/1668), P(GD102/09/H042), S, Z(MSM0021630528)
n3:dodaniDat
n20:2011
n3:domaciTvurceVysledku
n16:7825668 n16:8564892 n16:1196332
n3:druhVysledku
n18:D
n3:duvernostUdaju
n4:S
n3:entitaPredkladatele
n9:predkladatel
n3:idSjednocenehoVysledku
258879
n3:idVysledku
RIV/00216305:26230/10:PU89530
n3:jazykVysledku
n14:eng
n3:klicovaSlova
fault tolerant systems, reconfiguration, controller, FPGA, architecture
n3:klicoveSlovo
n7:controller n7:FPGA n7:fault%20tolerant%20systems n7:reconfiguration n7:architecture
n3:kontrolniKodProRIV
[B57BDAA56E1E]
n3:mistoKonaniAkce
Lille
n3:mistoVydani
Lille
n3:nazevZdroje
13th EUROMICRO Conference on Digital System Design, DSD'2010
n3:obor
n11:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n13:GA102%2F09%2F1668 n13:GD102%2F09%2FH042
n3:rokUplatneniVysledku
n20:2010
n3:tvurceVysledku
Kaštil, Jan Straka, Martin Kotásek, Zdeněk
n3:typAkce
n19:WRD
n3:zahajeniAkce
2010-09-01+02:00
n3:zamer
n21:MSM0021630528
s:numberOfPages
8
n12:hasPublisher
IEEE Computer Society
n15:isbn
978-0-7695-4171-6
n22:organizacniJednotka
26230