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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F10%3APU89525%21RIV11-MSM-26230___
rdf:type
n12:Vysledek skos:Concept
dcterms:description
With the growing number of viruses and network attacks, Intrusion Detection Systems have to match a large set of regular expressions at multi-gigabit speed to detect malicious activities on the network. Many algorithms and architectures have been designed to accelerate pattern matching, but most of them can be used only for strings or a small set of regular expressions.  We propose new NFA--Split architecture, which reduces the amount of consumed FPGA resources in order to match larger set of regular expressions at multi-gigabit speed. The proposed reduction uses model of nondeterministic and deterministic automaton for effective mapping of regular expressions to FPGA. A new algorithm is designed to split the nondeterministic automaton transition table in order to map a part of the table into memory. The algorithm can place more than 49\% of transition table to memory, which reduces the amount of look-up tables by more than 43\% and flip-flops by more than 38\% for all selected sets of regular ex With the growing number of viruses and network attacks, Intrusion Detection Systems have to match a large set of regular expressions at multi-gigabit speed to detect malicious activities on the network. Many algorithms and architectures have been designed to accelerate pattern matching, but most of them can be used only for strings or a small set of regular expressions.  We propose new NFA--Split architecture, which reduces the amount of consumed FPGA resources in order to match larger set of regular expressions at multi-gigabit speed. The proposed reduction uses model of nondeterministic and deterministic automaton for effective mapping of regular expressions to FPGA. A new algorithm is designed to split the nondeterministic automaton transition table in order to map a part of the table into memory. The algorithm can place more than 49\% of transition table to memory, which reduces the amount of look-up tables by more than 43\% and flip-flops by more than 38\% for all selected sets of regular ex
dcterms:title
Efficient Mapping of Nondeterministic Automata to FPGA for Fast Regular Expression Matching Efficient Mapping of Nondeterministic Automata to FPGA for Fast Regular Expression Matching
skos:prefLabel
Efficient Mapping of Nondeterministic Automata to FPGA for Fast Regular Expression Matching Efficient Mapping of Nondeterministic Automata to FPGA for Fast Regular Expression Matching
skos:notation
RIV/00216305:26230/10:PU89525!RIV11-MSM-26230___
n3:aktivita
n6:S n6:Z
n3:aktivity
S, Z(MSM0021630528)
n3:dodaniDat
n4:2011
n3:domaciTvurceVysledku
n7:9452591 n7:3991385
n3:druhVysledku
n19:D
n3:duvernostUdaju
n11:S
n3:entitaPredkladatele
n9:predkladatel
n3:idSjednocenehoVysledku
256398
n3:idVysledku
RIV/00216305:26230/10:PU89525
n3:jazykVysledku
n21:eng
n3:klicovaSlova
FPGA, regular expressions, automaton, transition table<br>
n3:klicoveSlovo
n14:FPGA n14:automaton n14:transition%20table%3Cbr%3E n14:regular%20expressions
n3:kontrolniKodProRIV
[2148C3060AE6]
n3:mistoKonaniAkce
Vienna
n3:mistoVydani
Vienna
n3:nazevZdroje
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010
n3:obor
n17:IN
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:rokUplatneniVysledku
n4:2010
n3:tvurceVysledku
Kořenek, Jan Košař, Vlastimil
n3:typAkce
n20:WRD
n3:zahajeniAkce
2010-04-14+02:00
n3:zamer
n16:MSM0021630528
s:numberOfPages
6
n15:hasPublisher
IEEE Computer Society
n10:isbn
978-1-4244-6610-8
n18:organizacniJednotka
26230