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Statements

Subject Item

n2:RIV%2F00216305%3A26230%2F10%3APU89524%21RIV11-MSM-26230___

rdf:type

skos:Concept n17:Vysledek

dcterms:description

With the increased amount of data transferred by<br>computer networks, the amount of the malicious traffic also<br>increases and therefore it is necessary to protect networks<br>by security systems such as firewalls and Intrusion Detection<br>Systems (IDS) operating at multigigabit speeds. Pattern matching<br>is the time critical operation of current IDS. This paper deals<br>with the analysis of regular expressions used by modern IDS<br>to describe malicious traffic. According to our analysis, more<br>than 64 percent of regular expressions create Deterministic Finite<br>Automaton (DFA) with less than 20 percent of saturation of<br>the transition table which allows efficient implementation of<br>pattern matching into FPGA platform. We propose architecture<br>for fast pattern matching using perfect hashing suitable for<br>implementation into FPGA platform. The memory requirements<br>of presented architecture is closed to the theoretical minimum<br>for sparse transition tables. With the increased amount of data transferred by<br>computer networks, the amount of the malicious traffic also<br>increases and therefore it is necessary to protect networks<br>by security systems such as firewalls and Intrusion Detection<br>Systems (IDS) operating at multigigabit speeds. Pattern matching<br>is the time critical operation of current IDS. This paper deals<br>with the analysis of regular expressions used by modern IDS<br>to describe malicious traffic. According to our analysis, more<br>than 64 percent of regular expressions create Deterministic Finite<br>Automaton (DFA) with less than 20 percent of saturation of<br>the transition table which allows efficient implementation of<br>pattern matching into FPGA platform. We propose architecture<br>for fast pattern matching using perfect hashing suitable for<br>implementation into FPGA platform. The memory requirements<br>of presented architecture is closed to the theoretical minimum<br>for sparse transition tables.

dcterms:title

Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing

skos:prefLabel

Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing

skos:notation

RIV/00216305:26230/10:PU89524!RIV11-MSM-26230___

n3:aktivita

n12:Z n12:S

n3:aktivity

S, Z(MSM0021630528)

n3:dodaniDat

n10:2011

n3:domaciTvurceVysledku

n15:8564892 n15:9452591

n3:druhVysledku

n20:D

n3:duvernostUdaju

n16:S

n3:entitaPredkladatele

n9:predkladatel

n3:idSjednocenehoVysledku

261204

n3:idVysledku

RIV/00216305:26230/10:PU89524

n3:jazykVysledku

n7:eng

n3:klicovaSlova

Intrusion Detection, Perfect Hashing,hardware acceleration, Deterministic Finite Automata<br>

n3:klicoveSlovo

n8:Deterministic%20Finite%20Automata%3Cbr%3E n8:Intrusion%20Detection n8:Perfect%20Hashing n8:hardware%20acceleration

n3:kontrolniKodProRIV

[51A3C6D8E3F5]

n3:mistoKonaniAkce

Vienna

n3:mistoVydani

Vienna

n3:nazevZdroje

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010

n3:obor

n18:JC

n3:pocetDomacichTvurcuVysledku

2

n3:pocetTvurcuVysledku

2

n3:rokUplatneniVysledku

n10:2010

n3:tvurceVysledku

Kořenek, Jan Kaštil, Jan

n3:typAkce

n5:WRD

n3:zahajeniAkce

2010-04-14+02:00

n3:zamer

n11:MSM0021630528

s:numberOfPages

4

n19:hasPublisher

IEEE Computer Society

n13:isbn

978-1-4244-6610-8

n14:organizacniJednotka

26230