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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F10%3APU89522%21RIV14-MSM-26230___
rdf:type
n12:Vysledek skos:Concept
dcterms:description
Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure size for the family of decomposition architectures at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the Cartesian product nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed. Packet classification algorithms are widely used in network security devices. As network speeds are increasing, the demand for hardware acceleration of packet classification in FPGAs or ASICs is growing. Nowadays hardware architectures can achieve multigigabit speeds only at the cost of large data structures, which can not fit into the on-chip memory. We propose novel method how to reduce data structure size for the family of decomposition architectures at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the Cartesian product nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed.
dcterms:title
Memory Optimization for Packet Classification Algorithms in FPGA Memory Optimization for Packet Classification Algorithms in FPGA
skos:prefLabel
Memory Optimization for Packet Classification Algorithms in FPGA Memory Optimization for Packet Classification Algorithms in FPGA
skos:notation
RIV/00216305:26230/10:PU89522!RIV14-MSM-26230___
n4:aktivita
n19:Z
n4:aktivity
Z(MSM0021630528), Z(MSM6383917201)
n4:dodaniDat
n18:2014
n4:domaciTvurceVysledku
n6:9452591 n6:6647596
n4:druhVysledku
n15:D
n4:duvernostUdaju
n21:S
n4:entitaPredkladatele
n20:predkladatel
n4:idSjednocenehoVysledku
270328
n4:idVysledku
RIV/00216305:26230/10:PU89522
n4:jazykVysledku
n16:eng
n4:klicovaSlova
packet classification, sram, fpga, tcam
n4:klicoveSlovo
n7:packet%20classification n7:tcam n7:sram n7:fpga
n4:kontrolniKodProRIV
[68B698A053FF]
n4:mistoKonaniAkce
Vienna
n4:mistoVydani
Vídeň
n4:nazevZdroje
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
n4:obor
n5:IN
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
3
n4:rokUplatneniVysledku
n18:2010
n4:tvurceVysledku
Kořenek, Jan Puš, Viktor
n4:typAkce
n17:WRD
n4:zahajeniAkce
2010-04-14+02:00
n4:zamer
n10:MSM0021630528 n10:MSM6383917201
s:numberOfPages
4
n3:hasPublisher
IEEE Computer Society
n14:isbn
978-1-4244-6610-8
n13:organizacniJednotka
26230