This HTML5 document contains 51 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
n8http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n14http://localhost/temp/predkladatel/
n4http://purl.org/net/nknouf/ns/bibtex#
n13http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n7http://linked.opendata.cz/resource/domain/vavai/projekt/
n22http://linked.opendata.cz/ontology/domain/vavai/
n20https://schema.org/
n15http://linked.opendata.cz/resource/domain/vavai/zamer/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
n19http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F00216305%3A26230%2F10%3APU89502%21RIV11-GA0-26230___/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n16http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n10http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n17http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n5http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n18http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n11http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n6http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F10%3APU89502%21RIV11-GA0-26230___
rdf:type
skos:Concept n22:Vysledek
dcterms:description
<p align=left>Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components. <p align=left>Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration process of the faulty unit are introduced as well. The modification of fault tolerant architectures into partial reconfigurable modules and main advantages of partial dynamic reconfiguration when used in fault tolerant system design are demonstrated. All presented architectures are compared with each other and proven fully functional on the ML506 development board with Virtex5 for different types of RTL digital components.
dcterms:title
Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs
skos:prefLabel
Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs
skos:notation
RIV/00216305:26230/10:PU89502!RIV11-GA0-26230___
n3:aktivita
n5:P n5:Z n5:S
n3:aktivity
P(GA102/09/1668), P(GD102/09/H042), S, Z(MSM0021630528)
n3:dodaniDat
n6:2011
n3:domaciTvurceVysledku
n13:1196332 n13:8564892 n13:7825668
n3:druhVysledku
n18:D
n3:duvernostUdaju
n10:S
n3:entitaPredkladatele
n19:predkladatel
n3:idSjednocenehoVysledku
272143
n3:idVysledku
RIV/00216305:26230/10:PU89502
n3:jazykVysledku
n17:eng
n3:klicovaSlova
fault tolerant, on-line checker, architecture, triple modular redundancy, duplex, FPGA, partial reconfiguration
n3:klicoveSlovo
n16:architecture n16:fault%20tolerant n16:triple%20modular%20redundancy n16:on-line%20checker n16:partial%20reconfiguration n16:duplex n16:FPGA
n3:kontrolniKodProRIV
[46F5F15A7B97]
n3:mistoKonaniAkce
Vienna
n3:mistoVydani
Wien
n3:nazevZdroje
Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010
n3:obor
n11:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n7:GD102%2F09%2FH042 n7:GA102%2F09%2F1668
n3:rokUplatneniVysledku
n6:2010
n3:tvurceVysledku
Kotásek, Zdeněk Straka, Martin Kaštil, Jan
n3:typAkce
n8:WRD
n3:zahajeniAkce
2010-04-14+02:00
n3:zamer
n15:MSM0021630528
s:numberOfPages
4
n4:hasPublisher
IEEE Computer Society
n20:isbn
978-1-4244-6610-8
n14:organizacniJednotka
26230