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Namespace Prefixes

PrefixIRI
dctermshttp://purl.org/dc/terms/
n20http://localhost/temp/predkladatel/
n17http://linked.opendata.cz/resource/domain/vavai/projekt/
n11http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n9http://linked.opendata.cz/ontology/domain/vavai/
n14http://linked.opendata.cz/resource/domain/vavai/zamer/
rdfshttp://www.w3.org/2000/01/rdf-schema#
skoshttp://www.w3.org/2004/02/skos/core#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n8http://linked.opendata.cz/ontology/domain/vavai/riv/licencniPoplatek/
n21http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F00216305%3A26230%2F10%3APR25258%21RIV12-GA0-26230___/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n10http://linked.opendata.cz/ontology/domain/vavai/riv/vyuzitiJinymSubjektem/
n7http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n4http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n19http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n12http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n18http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n15http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n13http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F10%3APR25258%21RIV12-GA0-26230___
rdf:type
n9:Vysledek skos:Concept
rdfs:seeAlso
http://www.fit.vutbr.cz/~smrcka/w/doku.php?id=research:cdcreloaded
dcterms:description
Conventional technique of hardware design formal verification is based on modelling zero-delay changes of signal value. Unfortunatelly, this type of abstraction hides the problem of clock domain crossings (CDCs) which cause is either in metastability or in a synchronization protocol design. CDCreloaded is a framework which gathers all one need for formal verification and analysis of hardware designs including asynchronous components. The framework consists of several components including (i) the tool cdcreveal for detection and extending of parts of a design prone to CDC problems, (ii) the tool envgen for generating an environment of a verified component, and (iii) the tool for niCE for building a filtered content of a counter-example to make the analysis of a discovered fault easier for a QA engineer. Conventional technique of hardware design formal verification is based on modelling zero-delay changes of signal value. Unfortunatelly, this type of abstraction hides the problem of clock domain crossings (CDCs) which cause is either in metastability or in a synchronization protocol design. CDCreloaded is a framework which gathers all one need for formal verification and analysis of hardware designs including asynchronous components. The framework consists of several components including (i) the tool cdcreveal for detection and extending of parts of a design prone to CDC problems, (ii) the tool envgen for generating an environment of a verified component, and (iii) the tool for niCE for building a filtered content of a counter-example to make the analysis of a discovered fault easier for a QA engineer.
dcterms:title
Framework for Formal Verification of Clock Domain Crossing Framework for Formal Verification of Clock Domain Crossing
skos:prefLabel
Framework for Formal Verification of Clock Domain Crossing Framework for Formal Verification of Clock Domain Crossing
skos:notation
RIV/00216305:26230/10:PR25258!RIV12-GA0-26230___
n3:aktivita
n19:P n19:Z
n3:aktivity
P(GAP103/10/0306), Z(MSM0021630528)
n3:dodaniDat
n13:2012
n3:domaciTvurceVysledku
n11:1458841 n11:9761985
n3:druhVysledku
n18:R
n3:duvernostUdaju
n4:S
n3:ekonomickeParametry
Volně šiřitelný software poskytovaný pod licencí GNU GPL v3.
n3:entitaPredkladatele
n21:predkladatel
n3:idSjednocenehoVysledku
259731
n3:idVysledku
RIV/00216305:26230/10:PR25258
n3:interniIdentifikace
cdcreloaded
n3:jazykVysledku
n12:eng
n3:klicovaSlova
clock-domain crossing, formal verification, environment specification
n3:klicoveSlovo
n7:formal%20verification n7:environment%20specification n7:clock-domain%20crossing
n3:kontrolniKodProRIV
[FF9A0DF2B977]
n3:licencniPoplatek
n8:N
n3:lokalizaceVysledku
http://www.fit.vutbr.cz/~smrcka/w/doku.php?id=research:cdcreloaded
n3:obor
n15:IN
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n17:GAP103%2F10%2F0306
n3:rokUplatneniVysledku
n13:2010
n3:technickeParametry
Čtyři nástroje v objektově-orientovaném návrhu v jazyku Python (verze vyšší nebo rovno 2.5 a nižší než 3.0) s otevřeným kódem. Nástroje slouží jako rozhraní příkazové řádky ke knihovnám implementující danou funkci. Programy a knihovny jsou použitelné pro všechny platformy podporující interpret jazyka Python. Rozsah všech zdrojových kódů včetně testů je cca 9 tisíc řádků. Volně šiřitelný software poskytovaný pod licencí GNU GPL v3, její znění je na http://www.gnu.org/licenses/gpl-3.0.txt.
n3:tvurceVysledku
Vojnar, Tomáš Smrčka, Aleš
n3:vlastnik
n21:vlastnikVysledku
n3:vyuzitiJinymSubjektem
n10:A
n3:zamer
n14:MSM0021630528
n20:organizacniJednotka
26230