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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F09%3APU86226%21RIV14-MSM-26230___
rdf:type
n8:Vysledek skos:Concept
dcterms:description
We propose novel method how to reduce data structure size for the family of packet classification algorithms at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the crossproduct nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed. We propose novel method how to reduce data structure size for the family of packet classification algorithms at the cost of additional pipelined processing with only small amount of logic resources. The reduction significantly decreases overhead given by the crossproduct nature of classification rules. Therefore the data structure can be compressed to 10 % on average. As high compression ratio is achieved, fast on-chip memory can be used to store data structures and hardware architectures can process network traffic at significantly higher speed.
dcterms:title
Memory Optimization for Packet Classification Algorithms Memory Optimization for Packet Classification Algorithms
skos:prefLabel
Memory Optimization for Packet Classification Algorithms Memory Optimization for Packet Classification Algorithms
skos:notation
RIV/00216305:26230/09:PU86226!RIV14-MSM-26230___
n4:aktivita
n18:Z
n4:aktivity
Z(MSM0021630528), Z(MSM6383917201)
n4:dodaniDat
n15:2014
n4:domaciTvurceVysledku
n7:9452591 n7:6647596
n4:druhVysledku
n16:D
n4:duvernostUdaju
n20:S
n4:entitaPredkladatele
n9:predkladatel
n4:idSjednocenehoVysledku
325318
n4:idVysledku
RIV/00216305:26230/09:PU86226
n4:jazykVysledku
n10:eng
n4:klicovaSlova
Packet Classification, FPGA, SRAM, Optimization
n4:klicoveSlovo
n5:Optimization n5:Packet%20Classification n5:SRAM n5:FPGA
n4:kontrolniKodProRIV
[F7231374F9C8]
n4:mistoKonaniAkce
Princeton
n4:mistoVydani
New York
n4:nazevZdroje
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
n4:obor
n13:JC
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
3
n4:rokUplatneniVysledku
n15:2009
n4:tvurceVysledku
Kořenek, Jan Puš, Viktor
n4:typAkce
n21:WRD
n4:zahajeniAkce
2009-10-19+02:00
n4:zamer
n6:MSM0021630528 n6:MSM6383917201
s:numberOfPages
2
n17:hasPublisher
Association for Computing Machinery
n14:isbn
978-1-60558-630-4
n11:organizacniJednotka
26230