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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F09%3APU82617%21RIV10-MSM-26230___
rdf:type
skos:Concept n21:Vysledek
dcterms:description
Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them can compete with the speed of TCAMs in the worst case. We propose new hardware-based algorithm for packet classification. The solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. The algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved. This makes throughput of 100 Gbps for the shortest packets. Further performance scaling is possible with more or faster SRAM chips. Packet classification is an important operation for applications such as routers, firewalls or intrusion detection systems. Many algorithms and hardware architectures for packet classification have been created, but none of them can compete with the speed of TCAMs in the worst case. We propose new hardware-based algorithm for packet classification. The solution is based on problem decomposition and is aimed at the highest network speeds. A unique property of the algorithm is the constant time complexity in terms of external memory accesses. The algorithm performs exactly two external memory accesses to classify a packet. Using FPGA and one commodity SRAM chip, a throughput of 150 million packets per second can be achieved. This makes throughput of 100 Gbps for the shortest packets. Further performance scaling is possible with more or faster SRAM chips.
dcterms:title
Fast and scalable packet classification using perfect hash functions Fast and scalable packet classification using perfect hash functions
skos:prefLabel
Fast and scalable packet classification using perfect hash functions Fast and scalable packet classification using perfect hash functions
skos:notation
RIV/00216305:26230/09:PU82617!RIV10-MSM-26230___
n3:aktivita
n7:Z
n3:aktivity
Z(MSM0021630528), Z(MSM6383917201)
n3:dodaniDat
n12:2010
n3:domaciTvurceVysledku
n5:9452591 n5:6647596
n3:druhVysledku
n13:D
n3:duvernostUdaju
n20:S
n3:entitaPredkladatele
n10:predkladatel
n3:idSjednocenehoVysledku
314691
n3:idVysledku
RIV/00216305:26230/09:PU82617
n3:jazykVysledku
n16:eng
n3:klicovaSlova
classification, FPGA, perfect hash function
n3:klicoveSlovo
n8:perfect%20hash%20function n8:classification n8:FPGA
n3:kontrolniKodProRIV
[1AFFDD08F3B3]
n3:mistoKonaniAkce
Monterey, Californi
n3:mistoVydani
New York
n3:nazevZdroje
Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays
n3:obor
n14:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:rokUplatneniVysledku
n12:2009
n3:tvurceVysledku
Kořenek, Jan Puš, Viktor
n3:typAkce
n17:WRD
n3:zahajeniAkce
2009-01-20+01:00
n3:zamer
n4:MSM6383917201 n4:MSM0021630528
s:numberOfPages
8
n15:hasPublisher
Association for Computing Machinery
n11:isbn
978-1-60558-410-2
n18:organizacniJednotka
26230