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Namespace Prefixes

PrefixIRI
n20http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n13http://localhost/temp/predkladatel/
n9http://purl.org/net/nknouf/ns/bibtex#
n15http://linked.opendata.cz/resource/domain/vavai/projekt/
n14http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n3http://linked.opendata.cz/ontology/domain/vavai/
n17http://linked.opendata.cz/resource/domain/vavai/zamer/
n10https://schema.org/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n5http://linked.opendata.cz/ontology/domain/vavai/riv/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n22http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F00216305%3A26230%2F09%3APU82605%21RIV11-GA0-26230___/
n6http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n11http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n19http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n7http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n21http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n16http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n18http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F09%3APU82605%21RIV11-GA0-26230___
rdf:type
n3:Vysledek skos:Concept
dcterms:description
In the paper, the methodology of fault tolerant systems design based on FPGA are presented. The architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the fault tolerant system is implemented. The principles of generating sequence of FT architectures with different level of diagnostic are presented. In the paper, the methodology of fault tolerant systems design based on FPGA are presented. The architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the fault tolerant system is implemented. The principles of generating sequence of FT architectures with different level of diagnostic are presented.
dcterms:title
High Availability Fault Tolerant Architectures Implemented into FPGAs High Availability Fault Tolerant Architectures Implemented into FPGAs
skos:prefLabel
High Availability Fault Tolerant Architectures Implemented into FPGAs High Availability Fault Tolerant Architectures Implemented into FPGAs
skos:notation
RIV/00216305:26230/09:PU82605!RIV11-GA0-26230___
n5:aktivita
n7:Z n7:P
n5:aktivity
P(GA102/09/1668), P(GD102/09/H042), Z(MSM0021630528)
n5:dodaniDat
n18:2011
n5:domaciTvurceVysledku
n14:7825668 n14:1196332
n5:druhVysledku
n21:D
n5:duvernostUdaju
n11:S
n5:entitaPredkladatele
n22:predkladatel
n5:idSjednocenehoVysledku
317079
n5:idVysledku
RIV/00216305:26230/09:PU82605
n5:jazykVysledku
n19:eng
n5:klicovaSlova
TMR, availability,&nbsp,Markov reliability model, FPGA, fault tolerant systems, checker
n5:klicoveSlovo
n6:Markov%20reliability%20model n6:FPGA n6:TMR n6:availability n6:fault%20tolerant%20systems n6:checker n6:%26nbsp
n5:kontrolniKodProRIV
[905F7F6339A1]
n5:mistoKonaniAkce
Patras
n5:mistoVydani
Patras
n5:nazevZdroje
12th EUROMICRO Conference on Digital System Design DSD 2009
n5:obor
n16:JC
n5:pocetDomacichTvurcuVysledku
2
n5:pocetTvurcuVysledku
2
n5:projekt
n15:GD102%2F09%2FH042 n15:GA102%2F09%2F1668
n5:rokUplatneniVysledku
n18:2009
n5:tvurceVysledku
Straka, Martin Kotásek, Zdeněk
n5:typAkce
n20:WRD
n5:zahajeniAkce
2009-08-27+02:00
n5:zamer
n17:MSM0021630528
s:numberOfPages
8
n9:hasPublisher
IEEE Computer Society
n10:isbn
978-0-7695-3782-5
n13:organizacniJednotka
26230