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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F09%3APU82602%21RIV10-MSM-26230___
rdf:type
skos:Concept n20:Vysledek
dcterms:description
Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing is required. We propose a new architecture of packet header analysis and fields extraction intended for high-speed FPGA-based network applications. The architecture is able to process 20 Gbps network links with less than 12 percent of available resources of Virtex 5 110 FPGA. Moreover, the presented solution can balance between network throughput and consumed hardware resources to fit application needs. The architecture for packet header processing is generated from standard XML protocol scheme and is strongly optimised for resource consumption and speed by an automatic HDL code   generator. Our solution also enables to change the set of extracted header fields on-line without FPGA reconfiguration. Packet header analysis and extraction of header fields needs to be performed in all network devices. As network speed is increasing quickly, high speed packet header processing is required. We propose a new architecture of packet header analysis and fields extraction intended for high-speed FPGA-based network applications. The architecture is able to process 20 Gbps network links with less than 12 percent of available resources of Virtex 5 110 FPGA. Moreover, the presented solution can balance between network throughput and consumed hardware resources to fit application needs. The architecture for packet header processing is generated from standard XML protocol scheme and is strongly optimised for resource consumption and speed by an automatic HDL code   generator. Our solution also enables to change the set of extracted header fields on-line without FPGA reconfiguration.
dcterms:title
Packet Header Analysis and Field Extraction for Multigigabit Networks Packet Header Analysis and Field Extraction for Multigigabit Networks
skos:prefLabel
Packet Header Analysis and Field Extraction for Multigigabit Networks Packet Header Analysis and Field Extraction for Multigigabit Networks
skos:notation
RIV/00216305:26230/09:PU82602!RIV10-MSM-26230___
n3:aktivita
n19:Z
n3:aktivity
Z(MSM0021630528), Z(MSM6383917201)
n3:dodaniDat
n8:2010
n3:domaciTvurceVysledku
n7:9452591 n7:9244492 n7:4920570
n3:druhVysledku
n13:D
n3:duvernostUdaju
n21:S
n3:entitaPredkladatele
n12:predkladatel
n3:idSjednocenehoVysledku
332517
n3:idVysledku
RIV/00216305:26230/09:PU82602
n3:jazykVysledku
n15:eng
n3:klicovaSlova
protocol analysis, extraction, networks, XML, FPGA<br>
n3:klicoveSlovo
n4:protocol%20analysis n4:XML n4:extraction n4:FPGA%3Cbr%3E n4:networks
n3:kontrolniKodProRIV
[6FF14EC65CDD]
n3:mistoKonaniAkce
Liberec
n3:mistoVydani
Liberec
n3:nazevZdroje
Proceedings of the 2009 IEEE Symphosium on Design and Diagnostics of Electronic Circuits and Systems
n3:obor
n11:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:rokUplatneniVysledku
n8:2009
n3:tvurceVysledku
Polčák, Libor Kořenek, Jan Kobierský, Petr
n3:typAkce
n14:WRD
n3:zahajeniAkce
2009-04-15+02:00
n3:zamer
n9:MSM6383917201 n9:MSM0021630528
s:numberOfPages
277
n18:hasPublisher
IEEE Computer Society
n10:isbn
978-1-4244-3339-1
n17:organizacniJednotka
26230