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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F09%3APU82587%21RIV10-MSM-26230___
rdf:type
skos:Concept n22:Vysledek
dcterms:description
In this paper, a new reconfigurable polymorphic chip (REPOMO32) is introduced. This chip has been developed in order to investigate the electrical properties of polymorphic circuits and demonstrate the applications of polymorphic electronics. REPOMO32 contains an array of 32 configurable logic elements; each of them can perform the AND, OR, XOR and polymorphic NAND/NOR function which is  controlled by the level of the power supply voltage. REPOMO32 parameters are reported together with the analysis of  polymorphic circuits implemented and evolved in REPOMO32. Potential applications of the chip are also discussed. In this paper, a new reconfigurable polymorphic chip (REPOMO32) is introduced. This chip has been developed in order to investigate the electrical properties of polymorphic circuits and demonstrate the applications of polymorphic electronics. REPOMO32 contains an array of 32 configurable logic elements; each of them can perform the AND, OR, XOR and polymorphic NAND/NOR function which is  controlled by the level of the power supply voltage. REPOMO32 parameters are reported together with the analysis of  polymorphic circuits implemented and evolved in REPOMO32. Potential applications of the chip are also discussed.
dcterms:title
REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware
skos:prefLabel
REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware
skos:notation
RIV/00216305:26230/09:PU82587!RIV10-MSM-26230___
n3:aktivita
n20:Z n20:P
n3:aktivity
P(GA102/06/0599), Z(MSM0021630528)
n3:dodaniDat
n18:2010
n3:domaciTvurceVysledku
n4:7619464 n4:7173873 n4:6455719 n4:3071138 n4:3760707
n3:druhVysledku
n5:D
n3:duvernostUdaju
n17:S
n3:entitaPredkladatele
n14:predkladatel
n3:idSjednocenehoVysledku
338989
n3:idVysledku
RIV/00216305:26230/09:PU82587
n3:jazykVysledku
n11:eng
n3:klicovaSlova
ASIC, polymorphic gate, evolvable hardware
n3:klicoveSlovo
n9:evolvable%20hardware n9:ASIC n9:polymorphic%20gate
n3:kontrolniKodProRIV
[3EDACE581B70]
n3:mistoKonaniAkce
Nashville
n3:mistoVydani
Nashville
n3:nazevZdroje
Proc. of the 2009 IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware
n3:obor
n6:JC
n3:pocetDomacichTvurcuVysledku
5
n3:pocetTvurcuVysledku
5
n3:projekt
n15:GA102%2F06%2F0599
n3:rokUplatneniVysledku
n18:2009
n3:tvurceVysledku
Prokop, Roman Vašíček, Zdeněk Sekanina, Lukáš Růžička, Richard Fujcik, Lukáš
n3:typAkce
n16:WRD
n3:zahajeniAkce
2009-03-30+02:00
n3:zamer
n10:MSM0021630528
s:numberOfPages
8
n7:hasPublisher
IEEE Computational Intelligence Society
n19:isbn
978-1-4244-2755-0
n8:organizacniJednotka
26230