This HTML5 document contains 44 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
dctermshttp://purl.org/dc/terms/
n6http://localhost/temp/predkladatel/
n17http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n14http://linked.opendata.cz/resource/domain/vavai/projekt/
n20http://linked.opendata.cz/ontology/domain/vavai/
n19http://linked.opendata.cz/ontology/domain/vavai/riv/podDruhVysledku/
n10http://linked.opendata.cz/resource/domain/vavai/zamer/
skoshttp://www.w3.org/2004/02/skos/core#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n13http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F00216305%3A26230%2F09%3APR24513%21RIV10-MSM-26230___/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n11http://linked.opendata.cz/ontology/domain/vavai/riv/kategorie/
n5http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n4http://linked.opendata.cz/ontology/domain/vavai/riv/vyuzitiJinymSubjektem/
n12http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n18http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n8http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n7http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n16http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F09%3APR24513%21RIV10-MSM-26230___
rdf:type
skos:Concept n20:Vysledek
dcterms:description
The EHWFILTER accelerator was developed in order to accelerate image filter evolution in hardware. It can automatically create a filter (e.g., to suppress shot noise) when noised image and uncorrupted original image are provided. The accelerator is implemented on the COMBO6X card equipped with Virtex II Pro 2VP50ff1517 FPGA. It consists of genetic unit, fitness unit and the so-called virtual reconfigurable circuit (VRC) which is utilized to evaluate candidate filters. Every image filter is considered as a digital circuit of nine 8-bit inputs and a single 8-bit output, which processes grayscale (8-bits/pixel) images. Training images are stored in external SRAM memories. The search algorithm is based on Cartesian Genetic Programming operating over 4x8 programmable elements, population size of 8 individuals, and 1 mutation/chromosome. This setting is default but can be changed. The accelerator is connected with PC using PCI bus. The system requires approx. 10 sec to produce a filter which is 44 The EHWFILTER accelerator was developed in order to accelerate image filter evolution in hardware. It can automatically create a filter (e.g., to suppress shot noise) when noised image and uncorrupted original image are provided. The accelerator is implemented on the COMBO6X card equipped with Virtex II Pro 2VP50ff1517 FPGA. It consists of genetic unit, fitness unit and the so-called virtual reconfigurable circuit (VRC) which is utilized to evaluate candidate filters. Every image filter is considered as a digital circuit of nine 8-bit inputs and a single 8-bit output, which processes grayscale (8-bits/pixel) images. Training images are stored in external SRAM memories. The search algorithm is based on Cartesian Genetic Programming operating over 4x8 programmable elements, population size of 8 individuals, and 1 mutation/chromosome. This setting is default but can be changed. The accelerator is connected with PC using PCI bus. The system requires approx. 10 sec to produce a filter which is 44
dcterms:title
Hardware Accelerator for Evolutionary Image Filters Design Hardware Accelerator for Evolutionary Image Filters Design
skos:prefLabel
Hardware Accelerator for Evolutionary Image Filters Design Hardware Accelerator for Evolutionary Image Filters Design
skos:notation
RIV/00216305:26230/09:PR24513!RIV10-MSM-26230___
n3:aktivita
n8:P n8:Z
n3:aktivity
P(GA102/07/0850), Z(MSM0021630528)
n3:dodaniDat
n16:2010
n3:domaciTvurceVysledku
n17:6455719 n17:7173873
n3:druhVysledku
n19:G%2FB
n3:duvernostUdaju
n12:S
n3:ekonomickeParametry
Cena závisí na počtu odebíraných kusů.
n3:entitaPredkladatele
n13:predkladatel
n3:idSjednocenehoVysledku
316850
n3:idVysledku
RIV/00216305:26230/09:PR24513
n3:interniIdentifikace
EHWFILTER
n3:jazykVysledku
n18:eng
n3:kategorie
n11:A
n3:klicovaSlova
accelerator, FPGA, Combo6X, evolutionary algorithm, image filter
n3:klicoveSlovo
n5:evolutionary%20algorithm n5:FPGA n5:accelerator n5:image%20filter n5:Combo6X
n3:kontrolniKodProRIV
[B6D3FB839E2C]
n3:lokalizaceVysledku
Ústav počítačových systémů, Fakulta informačních technologií VUT v Brně, Božetěchova 2, 612 66 Brno, http://www.fit.vutbr.cz/units/UPSY/
n3:obor
n7:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n14:GA102%2F07%2F0850
n3:rokUplatneniVysledku
n16:2009
n3:technickeParametry
Akcelerátor je implementován na kartě COMBO6X vybavené FPGA Virtex II Pro 2VP50ff1517 obsahující procesor PowerPC. Interně procesor pracuje na 300 MHz, podpůrná logika na 150 MHz. Ostatní komponenty akcelerátoru (virtuální rekonfigurovateln
n3:tvurceVysledku
Sekanina, Lukáš Vašíček, Zdeněk
n3:vlastnik
n13:vlastnikVysledku
n3:vyuzitiJinymSubjektem
n4:N
n3:zamer
n10:MSM0021630528
n6:organizacniJednotka
26230