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Statements

Subject Item

n2:RIV%2F00216305%3A26230%2F08%3APU78065%21RIV10-MSM-26230___

rdf:type

skos:Concept n12:Vysledek

dcterms:description

Packet classification is an important operation for applications such as<br>routers, firewalls or intrusion detection systems. Many algorithms and<br>hardware architectures for packet classification have been created, but<br>none of them can compete with the speed of TCAMs in the worst case. <br>I propose new<br>hardware-based algorithm for packet classification. The solution is based<br>on problem decomposition and is aimed at the highest network speeds. A unique<br>property of the algorithm is the constant time complexity in terms of<br>external memory accesses. The algorithm performs exactly two external<br>memory accesses to classify a packet. Using FPGA and one commodity SRAM<br>chip, a throughput of 150 million packets per second can be achieved. Packet classification is an important operation for applications such as<br>routers, firewalls or intrusion detection systems. Many algorithms and<br>hardware architectures for packet classification have been created, but<br>none of them can compete with the speed of TCAMs in the worst case. <br>I propose new<br>hardware-based algorithm for packet classification. The solution is based<br>on problem decomposition and is aimed at the highest network speeds. A unique<br>property of the algorithm is the constant time complexity in terms of<br>external memory accesses. The algorithm performs exactly two external<br>memory accesses to classify a packet. Using FPGA and one commodity SRAM<br>chip, a throughput of 150 million packets per second can be achieved.

dcterms:title

Fast Packet Classification Using Perfect Hash Functions Fast Packet Classification Using Perfect Hash Functions

skos:prefLabel

Fast Packet Classification Using Perfect Hash Functions Fast Packet Classification Using Perfect Hash Functions

skos:notation

RIV/00216305:26230/08:PU78065!RIV10-MSM-26230___

n3:aktivita

n21:Z

n3:aktivity

Z(MSM0021630528)

n3:dodaniDat

n7:2010

n3:domaciTvurceVysledku

n10:6647596

n3:druhVysledku

n15:D

n3:duvernostUdaju

n5:S

n3:entitaPredkladatele

n20:predkladatel

n3:idSjednocenehoVysledku

367696

n3:idVysledku

RIV/00216305:26230/08:PU78065

n3:jazykVysledku

n11:eng

n3:klicovaSlova

FPGA, Hardware, Firewall

n3:klicoveSlovo

n4:Hardware n4:Firewall n4:FPGA

n3:kontrolniKodProRIV

[D70F8C8FF057]

n3:mistoKonaniAkce

Praha

n3:mistoVydani

Praha

n3:nazevZdroje

ACM Student Research Competition 2008

n3:obor

n17:JC

n3:pocetDomacichTvurcuVysledku

1

n3:pocetTvurcuVysledku

1

n3:rokUplatneniVysledku

n7:2008

n3:tvurceVysledku

Puš, Viktor

n3:typAkce

n14:CST

n3:zahajeniAkce

2006-11-28+01:00

n3:zamer

n9:MSM0021630528

s:numberOfPages

8

n16:hasPublisher

Neuveden

n13:isbn

978-80-01-04205-2

n18:organizacniJednotka

26230