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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F08%3APU78052%21RIV10-MSM-26230___
rdf:type
skos:Concept n19:Vysledek
dcterms:description
The division of an application between a conventional processor and an acceleration card with FPGA chips has been proved as a suitable way for an acceleration of computationally intensive tasks. In such applications, the designer usually has to implement an interconnection between components placed in FPGA and the host system bus. This task is often complicated by different requirements of user components for throughput, latency of reading operations, need for DMA transfers etc. The objective of this work is to show a new approach for implementation of interconnection systems and to enable the designer to focus on the development of the target application.  The proposed interconnection system is based on tree topology. The system eliminates the sensitivity of wide buses to the distance, supports the connection of components with different requirements for throughput, supports split transaction model and many other features. The proposed system is implemented and evaluated on chips with Virtex 5 t The division of an application between a conventional processor and an acceleration card with FPGA chips has been proved as a suitable way for an acceleration of computationally intensive tasks. In such applications, the designer usually has to implement an interconnection between components placed in FPGA and the host system bus. This task is often complicated by different requirements of user components for throughput, latency of reading operations, need for DMA transfers etc. The objective of this work is to show a new approach for implementation of interconnection systems and to enable the designer to focus on the development of the target application.  The proposed interconnection system is based on tree topology. The system eliminates the sensitivity of wide buses to the distance, supports the connection of components with different requirements for throughput, supports split transaction model and many other features. The proposed system is implemented and evaluated on chips with Virtex 5 t
dcterms:title
GICS: Generic Interconnection System GICS: Generic Interconnection System
skos:prefLabel
GICS: Generic Interconnection System GICS: Generic Interconnection System
skos:notation
RIV/00216305:26230/08:PU78052!RIV10-MSM-26230___
n3:aktivita
n8:Z
n3:aktivity
Z(MSM0021630528)
n3:dodaniDat
n4:2010
n3:domaciTvurceVysledku
n14:7031971 n14:9452591 n14:4123484
n3:druhVysledku
n16:D
n3:duvernostUdaju
n12:S
n3:entitaPredkladatele
n17:predkladatel
n3:idSjednocenehoVysledku
369393
n3:idVysledku
RIV/00216305:26230/08:PU78052
n3:jazykVysledku
n18:eng
n3:klicovaSlova
Interconnection system, PCI Express, FPGA<br>
n3:klicoveSlovo
n5:PCI%20Express n5:FPGA%3Cbr%3E n5:Interconnection%20system
n3:kontrolniKodProRIV
[81754F3EF15D]
n3:mistoKonaniAkce
Heidelberg, Germany
n3:mistoVydani
Heidelberg
n3:nazevZdroje
2008 International Conference on Field Programmable Logic and Applications
n3:obor
n6:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:rokUplatneniVysledku
n4:2008
n3:tvurceVysledku
Martínek, Tomáš Kořenek, Jan Málek, Tomáš
n3:typAkce
n20:WRD
n3:zahajeniAkce
2008-09-08+02:00
n3:zamer
n21:MSM0021630528
s:numberOfPages
6
n7:hasPublisher
IEEE Computer Society
n10:isbn
978-1-4244-1960-9
n15:organizacniJednotka
26230