This HTML5 document contains 47 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
n12http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n6http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F00216305%3A26230%2F08%3APU78052%21RIV09-MSM-26230___/
n21http://localhost/temp/predkladatel/
n3http://purl.org/net/nknouf/ns/bibtex#
n10http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n15http://linked.opendata.cz/ontology/domain/vavai/
n13http://linked.opendata.cz/resource/domain/vavai/zamer/
n9https://schema.org/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n5http://linked.opendata.cz/ontology/domain/vavai/riv/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n16http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n20http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n11http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n7http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n19http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n17http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n18http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F08%3APU78052%21RIV09-MSM-26230___
rdf:type
skos:Concept n15:Vysledek
dcterms:description
Rozdělení aplikace mezi konvenční procesor a akcelerační kartu s FPGA čipy se ukázalo jako vhodný způsob pro akceleraci výpočetně náročných úloh. V těchto aplikacích, musí vyvojář obvykle implementovat propojovací systém mezi komponentami umístěnými v FPGA a systémovou sběrnicí. Tento úkol je však často komplikován různými požadavky ze strany uživatelských komponent např. na propustnost, latenci čtecích operací, potřeba DMA přenosů apod. Cílem této práce je ukázat nový přístup pro implementaci propojovacího systému a umožnit vývojáři se soustředit na vývoj cílové aplikace. Navrhovaný propojovací systém je založen na stromové architektuře, eliminuje citlivost na vzdálenost, podporuje připojení komponent s různými požadavky na propustnost, podporuje model rozdělených transakcí a mnoho dalších vlastností. Navrhovaný systém je implementován a ohodnocen na čipech s technologií Virtex 5.<br> The division of an application between a conventional processor and an acceleration card with FPGA chips has been proved as a suitable way for an acceleration of computationally intensive tasks. In such applications, the designer usually has to implement an interconnection between components placed in FPGA and the host system bus. This task is often complicated by different requirements of user components for throughput, latency of reading operations, need for DMA transfers etc. The objective of this work is to show a new approach for implementation of interconnection systems and to enable the designer to focus on the development of the target application.&nbsp; The proposed interconnection system is based on tree topology. The system eliminates the sensitivity of wide buses to the distance, supports the connection of components with different requirements for throughput, supports split transaction model and many other features. The proposed system is implemented and evaluated on chips with Virtex 5 t The division of an application between a conventional processor and an acceleration card with FPGA chips has been proved as a suitable way for an acceleration of computationally intensive tasks. In such applications, the designer usually has to implement an interconnection between components placed in FPGA and the host system bus. This task is often complicated by different requirements of user components for throughput, latency of reading operations, need for DMA transfers etc. The objective of this work is to show a new approach for implementation of interconnection systems and to enable the designer to focus on the development of the target application.&nbsp; The proposed interconnection system is based on tree topology. The system eliminates the sensitivity of wide buses to the distance, supports the connection of components with different requirements for throughput, supports split transaction model and many other features. The proposed system is implemented and evaluated on chips with Virtex 5 t
dcterms:title
GICS: Generic Interconnection System GICS: Generic Interconnection System GICS: Generický propojovací systém
skos:prefLabel
GICS: Generic Interconnection System GICS: Generický propojovací systém GICS: Generic Interconnection System
skos:notation
RIV/00216305:26230/08:PU78052!RIV09-MSM-26230___
n5:aktivita
n7:Z
n5:aktivity
Z(MSM0021630528), Z(MSM6383917201)
n5:dodaniDat
n18:2009
n5:domaciTvurceVysledku
n10:4123484 n10:9452591 n10:7031971
n5:druhVysledku
n17:D
n5:duvernostUdaju
n20:S
n5:entitaPredkladatele
n6:predkladatel
n5:idSjednocenehoVysledku
369394
n5:idVysledku
RIV/00216305:26230/08:PU78052
n5:jazykVysledku
n11:eng
n5:klicovaSlova
Interconnection system, PCI Express, FPGA<br>
n5:klicoveSlovo
n16:PCI%20Express n16:FPGA%3Cbr%3E n16:Interconnection%20system
n5:kontrolniKodProRIV
[35CABB032D02]
n5:mistoKonaniAkce
Heidelberg, Germany
n5:mistoVydani
Heidelberg
n5:nazevZdroje
2008 International Conference on Field Programmable Logic and Applications
n5:obor
n19:JC
n5:pocetDomacichTvurcuVysledku
3
n5:pocetTvurcuVysledku
3
n5:rokUplatneniVysledku
n18:2008
n5:tvurceVysledku
Málek, Tomáš Kořenek, Jan Martínek, Tomáš
n5:typAkce
n12:WRD
n5:zahajeniAkce
2008-09-08+02:00
n5:zamer
n13:MSM0021630528 n13:MSM6383917201
s:numberOfPages
6
n3:hasPublisher
IEEE Computer Society
n9:isbn
978-1-4244-1961-6
n21:organizacniJednotka
26230