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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F08%3APU76802%21RIV10-MSM-26230___
rdf:type
skos:Concept n19:Vysledek
dcterms:description
In this paper, the new methodology from areas fault tolerant systems based on automated generation of checkers in FPGA is presented. Dependability models of architectures based on the use of on-line checkers are described in the paper as well. First, the results of our research in the area of on-line checkers design are described. It is shown how the architectures with on-line checkers can be used in implementing dependable systems into FPGA and required dependability parameters. It is shown how the dependability parameters are derived from the architecture of the system and used for the design of dependable systems into XILINX FPGA. In this paper, the new methodology from areas fault tolerant systems based on automated generation of checkers in FPGA is presented. Dependability models of architectures based on the use of on-line checkers are described in the paper as well. First, the results of our research in the area of on-line checkers design are described. It is shown how the architectures with on-line checkers can be used in implementing dependable systems into FPGA and required dependability parameters. It is shown how the dependability parameters are derived from the architecture of the system and used for the design of dependable systems into XILINX FPGA.
dcterms:title
Design of FPGA-Based Dependable Systems Design of FPGA-Based Dependable Systems
skos:prefLabel
Design of FPGA-Based Dependable Systems Design of FPGA-Based Dependable Systems
skos:notation
RIV/00216305:26230/08:PU76802!RIV10-MSM-26230___
n3:aktivita
n8:Z n8:P
n3:aktivity
P(GD102/05/H050), Z(MSM0021630528)
n3:dodaniDat
n9:2010
n3:domaciTvurceVysledku
n12:7825668 n12:1196332
n3:druhVysledku
n20:D
n3:duvernostUdaju
n7:S
n3:entitaPredkladatele
n18:predkladatel
n3:idSjednocenehoVysledku
362682
n3:idVysledku
RIV/00216305:26230/08:PU76802
n3:jazykVysledku
n15:eng
n3:klicovaSlova
on-line checkers, fault tolerant systems,&nbsp,dependable systems, dependability parameters, dependability models, FPGA
n3:klicoveSlovo
n4:%26nbsp n4:fault%20tolerant%20systems n4:dependability%20models n4:dependability%20parameters n4:dependable%20systems n4:on-line%20checkers n4:FPGA
n3:kontrolniKodProRIV
[01B127644730]
n3:mistoKonaniAkce
Znojmo
n3:mistoVydani
Znojmo
n3:nazevZdroje
4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
n3:obor
n21:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n6:GD102%2F05%2FH050
n3:rokUplatneniVysledku
n9:2008
n3:tvurceVysledku
Straka, Martin Kotásek, Zdeněk
n3:typAkce
n13:WRD
n3:zahajeniAkce
2008-11-14+01:00
n3:zamer
n5:MSM0021630528
s:numberOfPages
8
n10:hasPublisher
Masaryk University
n22:isbn
978-80-7355-082-0
n16:organizacniJednotka
26230