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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F08%3APU76736%21RIV10-MSM-26230___
rdf:type
skos:Concept n15:Vysledek
dcterms:description
This article presents a new real-world application of evolutionary computing in the area of digital-circuits testing. A method is described which enables to evolve large synthetic RTL benchmark circuits with a predefined structure and testability. Using the proposed method, a new collection of synthetic benchmark circuits was developed. These benchmark circuits will be useful in a validation process of novel algorithms and tools in the area of digital-circuits testing. Evolved benchmark circuits currently represent the most complex benchmark circuits with a known level of testability. Furthermore, these circuits are the largest that have ever been designed by means of evolutionary algorithms. This work also investigates suitable parameters of the evolutionary algorithm for this problem and explores the limits in the complexity of evolved circuits. This article presents a new real-world application of evolutionary computing in the area of digital-circuits testing. A method is described which enables to evolve large synthetic RTL benchmark circuits with a predefined structure and testability. Using the proposed method, a new collection of synthetic benchmark circuits was developed. These benchmark circuits will be useful in a validation process of novel algorithms and tools in the area of digital-circuits testing. Evolved benchmark circuits currently represent the most complex benchmark circuits with a known level of testability. Furthermore, these circuits are the largest that have ever been designed by means of evolutionary algorithms. This work also investigates suitable parameters of the evolutionary algorithm for this problem and explores the limits in the complexity of evolved circuits.
dcterms:title
Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability
skos:prefLabel
Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability
skos:notation
RIV/00216305:26230/08:PU76736!RIV10-MSM-26230___
n3:aktivita
n13:Z n13:P
n3:aktivity
P(GA102/07/0850), P(GD102/05/H050), Z(MSM0021630528)
n3:cisloPeriodika
3
n3:dodaniDat
n7:2010
n3:domaciTvurceVysledku
n9:7173873 n9:1321196 n9:7825668
n3:druhVysledku
n17:J
n3:duvernostUdaju
n12:S
n3:entitaPredkladatele
n4:predkladatel
n3:idSjednocenehoVysledku
366942
n3:idVysledku
RIV/00216305:26230/08:PU76736
n3:jazykVysledku
n19:eng
n3:klicovaSlova
evolutionary algorithm, digital circuit, testability analysis
n3:klicoveSlovo
n14:digital%20circuit n14:evolutionary%20algorithm n14:testability%20analysis
n3:kodStatuVydavatele
US - Spojené státy americké
n3:kontrolniKodProRIV
[EE4A6F307651]
n3:nazevZdroje
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
n3:obor
n10:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n8:GD102%2F05%2FH050 n8:GA102%2F07%2F0850
n3:rokUplatneniVysledku
n7:2008
n3:svazekPeriodika
13
n3:tvurceVysledku
Sekanina, Lukáš Kotásek, Zdeněk Pečenka, Tomáš
n3:zamer
n18:MSM0021630528
s:issn
1084-4309
s:numberOfPages
21
n16:organizacniJednotka
26230