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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F08%3APU76701%21RIV10-MSM-26230___
rdf:type
skos:Concept n15:Vysledek
dcterms:description
<p align=left>A new FPGA implementation for adaptive median filters is proposed. Adaptive median filters exhibit better filtering properties than standard median filters; however, their implementation cost is higher. Proposed architecture was optimized for throughput allowing 300M pixels to be filtered per second. The best performance/cost ratio exhibits the adaptive median filter which utilizes filtering window 7x7 pixels and can suppress shot noise with intensity up to 60%. In addition to filtering, adaptive median filters can be also used as detectors of corrupted pixels (detection statistics). <p align=left>A new FPGA implementation for adaptive median filters is proposed. Adaptive median filters exhibit better filtering properties than standard median filters; however, their implementation cost is higher. Proposed architecture was optimized for throughput allowing 300M pixels to be filtered per second. The best performance/cost ratio exhibits the adaptive median filter which utilizes filtering window 7x7 pixels and can suppress shot noise with intensity up to 60%. In addition to filtering, adaptive median filters can be also used as detectors of corrupted pixels (detection statistics).
dcterms:title
Novel Hardware Implementation of Adaptive Median Filters Novel Hardware Implementation of Adaptive Median Filters
skos:prefLabel
Novel Hardware Implementation of Adaptive Median Filters Novel Hardware Implementation of Adaptive Median Filters
skos:notation
RIV/00216305:26230/08:PU76701!RIV10-MSM-26230___
n3:aktivita
n17:P n17:Z
n3:aktivity
P(GA102/07/0850), Z(MSM0021630528)
n3:dodaniDat
n16:2010
n3:domaciTvurceVysledku
n13:7173873 n13:6455719
n3:druhVysledku
n10:D
n3:duvernostUdaju
n21:S
n3:entitaPredkladatele
n22:predkladatel
n3:idSjednocenehoVysledku
383267
n3:idVysledku
RIV/00216305:26230/08:PU76701
n3:jazykVysledku
n12:eng
n3:klicovaSlova
adaptive median filter, image processing,&nbsp,FPGA,
n3:klicoveSlovo
n4:FPGA n4:image%20processing n4:%26nbsp n4:adaptive%20median%20filter
n3:kontrolniKodProRIV
[802DA3D422FF]
n3:mistoKonaniAkce
Bratislava
n3:mistoVydani
Bratislava
n3:nazevZdroje
Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
n3:obor
n18:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n20:GA102%2F07%2F0850
n3:rokUplatneniVysledku
n16:2008
n3:tvurceVysledku
Sekanina, Lukáš Vašíček, Zdeněk
n3:typAkce
n11:WRD
n3:zahajeniAkce
2008-04-16+02:00
n3:zamer
n14:MSM0021630528
s:numberOfPages
6
n19:hasPublisher
IEEE Computer Society
n6:isbn
978-1-4244-2276-0
n8:organizacniJednotka
26230