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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F08%3APR27617%21RIV14-MSM-26230___
rdf:type
n14:Vysledek skos:Concept
rdfs:seeAlso
http://www.fit.vutbr.cz/~strnadel/diag/taste
dcterms:description
TASTE (Testability Analysis SuiTE) is a library of C++ functions allowing a user to    - create a structural model of digital design:         - Each design is represented by an object of clsDesign class. It is           planned clsDesign object could consists of one ore more objects of           clsCircuit class, each of them representing particular circuit within           the design. In actual TASTE version, only one clsCircuit object is           supported within a clsDesign object. The disadvantage shoud be removed           in next TASTE version.         - Actually, clsCircuit object consists of one or more modules (objects of           clsModule class) forming a structure and transparency behavior of the           circuit.         - Next version of TASTE will be extended to modeling of hierarcical           designs.         - Interfaces are assigned to clsDesign / clsCircuit / clsModule objects           by means of clsPort and clsBit objects.         - Interconnections among clsDesign / clsCircuit / clsModule object           interfaces are represented by means of clsWire objects.         - Example functions for loading necessary structural and transparency           data are implemented in fileio.cc (header file fileio.h).    - run testability analysis (TA) over the modeled design:         - Functions for saving TA results in html, LaTEX and plain-text formats           are offered in actual version of TASTE library and available only to           clsCircuit objects. However, set of similar functions can be easily           extended to more classes, formats etc.         - Optionally, it is possible to implement scan chains (popular design for           testability (DFT) technique) into the original struct TASTE (Testability Analysis SuiTE) is a library of C++ functions allowing a user to    - create a structural model of digital design:         - Each design is represented by an object of clsDesign class. It is           planned clsDesign object could consists of one ore more objects of           clsCircuit class, each of them representing particular circuit within           the design. In actual TASTE version, only one clsCircuit object is           supported within a clsDesign object. The disadvantage shoud be removed           in next TASTE version.         - Actually, clsCircuit object consists of one or more modules (objects of           clsModule class) forming a structure and transparency behavior of the           circuit.         - Next version of TASTE will be extended to modeling of hierarcical           designs.         - Interfaces are assigned to clsDesign / clsCircuit / clsModule objects           by means of clsPort and clsBit objects.         - Interconnections among clsDesign / clsCircuit / clsModule object           interfaces are represented by means of clsWire objects.         - Example functions for loading necessary structural and transparency           data are implemented in fileio.cc (header file fileio.h).    - run testability analysis (TA) over the modeled design:         - Functions for saving TA results in html, LaTEX and plain-text formats           are offered in actual version of TASTE library and available only to           clsCircuit objects. However, set of similar functions can be easily           extended to more classes, formats etc.         - Optionally, it is possible to implement scan chains (popular design for           testability (DFT) technique) into the original struct
dcterms:title
TASTE: Testability Analysis SuiTE TASTE: Testability Analysis SuiTE
skos:prefLabel
TASTE: Testability Analysis SuiTE TASTE: Testability Analysis SuiTE
skos:notation
RIV/00216305:26230/08:PR27617!RIV14-MSM-26230___
n3:aktivita
n17:Z
n3:aktivity
Z(MSM0021630528)
n3:dodaniDat
n7:2014
n3:domaciTvurceVysledku
n18:8821968
n3:druhVysledku
n12:R
n3:duvernostUdaju
n13:S
n3:ekonomickeParametry
Software volně šiřitelný a využitelný v rozsahu daném licenčními podmínkami.
n3:entitaPredkladatele
n8:predkladatel
n3:idSjednocenehoVysledku
399044
n3:idVysledku
RIV/00216305:26230/08:PR27617
n3:interniIdentifikace
TASTE
n3:jazykVysledku
n9:eng
n3:klicovaSlova
digital, circuit, testability, analysis, scan, transparency, netlist, graph, model, searching, marking, reachability, library, component, template
n3:klicoveSlovo
n4:component n4:graph n4:digital n4:library n4:marking n4:model n4:circuit n4:testability n4:scan n4:template n4:analysis n4:searching n4:transparency n4:netlist n4:reachability
n3:kontrolniKodProRIV
[B5B7F25ABAB4]
n3:obor
n19:JC
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
1
n3:rokUplatneniVysledku
n7:2008
n3:technickeParametry
Požadavky pro instalaci a spuštění: překladač jazyka C++ vyhovující alespoň ISO/IEC 14882:2003.
n3:tvurceVysledku
Strnadel, Josef
n3:vlastnik
n8:vlastnikVysledku
n3:vyuzitiJinymSubjektem
n5:N
n3:zamer
n10:MSM0021630528
n6:organizacniJednotka
26230