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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F07%3APU70809%21RIV08-MSM-26230___
rdf:type
n7:Vysledek skos:Concept
dcterms:description
<p align=left>In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enabling to describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs. <p align=left>In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enabling to describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs. <p align=left>In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enabling to describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs.
dcterms:title
Checker Design for On-line Testing of Xilinx FPGA Communication Checker Design for On-line Testing of Xilinx FPGA Communication Checker Design for On-line Testing of Xilinx FPGA Communication
skos:prefLabel
Checker Design for On-line Testing of Xilinx FPGA Communication Checker Design for On-line Testing of Xilinx FPGA Communication Checker Design for On-line Testing of Xilinx FPGA Communication
skos:notation
RIV/00216305:26230/07:PU70809!RIV08-MSM-26230___
n4:strany
152-160
n4:aktivita
n12:Z n12:P
n4:aktivity
P(GD102/05/H050), Z(MSM0021630528)
n4:dodaniDat
n11:2008
n4:domaciTvurceVysledku
n6:7825668 n6:1196332 n6:5518288
n4:druhVysledku
n18:D
n4:duvernostUdaju
n9:S
n4:entitaPredkladatele
n10:predkladatel
n4:idSjednocenehoVysledku
413433
n4:idVysledku
RIV/00216305:26230/07:PU70809
n4:jazykVysledku
n17:eng
n4:klicovaSlova
Communication Protocol Testing, Fault Tolerant Systems,<br>checker design
n4:klicoveSlovo
n8:Fault%20Tolerant%20Systems n8:%3Cbr%3Echecker%20design n8:Communication%20Protocol%20Testing
n4:kontrolniKodProRIV
[A864CFBE2A57]
n4:mistoKonaniAkce
Rome
n4:mistoVydani
Rome
n4:nazevZdroje
The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
n4:obor
n14:JC
n4:pocetDomacichTvurcuVysledku
3
n4:pocetTvurcuVysledku
3
n4:projekt
n13:GD102%2F05%2FH050
n4:rokUplatneniVysledku
n11:2007
n4:tvurceVysledku
Tobola, Jiří Straka, Martin Kotásek, Zdeněk
n4:typAkce
n19:WRD
n4:zahajeniAkce
2007-09-26+02:00
n4:zamer
n20:MSM0021630528
s:numberOfPages
9
n16:hasPublisher
IEEE Computer Society
n22:isbn
0-7695-2885-6
n15:organizacniJednotka
26230