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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F07%3APU70806%21RIV08-MSM-26230___
rdf:type
skos:Concept n20:Vysledek
dcterms:description
In this paper, the methodology for automated design of checker for<br>communication protocol testing is presented. Based on the level of<br>checking, different design strategies can be performed - in the<br>paper the lowest level is presented. The definition of dedicated<br>language for the description of possible communication faults is<br>presented. The core generator is used to produce VHDL code<br>describing the behaviour of the checker. In this paper, the methodology for automated design of checker for<br>communication protocol testing is presented. Based on the level of<br>checking, different design strategies can be performed - in the<br>paper the lowest level is presented. The definition of dedicated<br>language for the description of possible communication faults is<br>presented. The core generator is used to produce VHDL code<br>describing the behaviour of the checker. In this paper, the methodology for automated design of checker for<br>communication protocol testing is presented. Based on the level of<br>checking, different design strategies can be performed - in the<br>paper the lowest level is presented. The definition of dedicated<br>language for the description of possible communication faults is<br>presented. The core generator is used to produce VHDL code<br>describing the behaviour of the checker.
dcterms:title
Online Protocol Testing for FPGA Based Fault Tolerant Systems Online Protocol Testing for FPGA Based Fault Tolerant Systems Online Protocol Testing for FPGA Based Fault Tolerant Systems
skos:prefLabel
Online Protocol Testing for FPGA Based Fault Tolerant Systems Online Protocol Testing for FPGA Based Fault Tolerant Systems Online Protocol Testing for FPGA Based Fault Tolerant Systems
skos:notation
RIV/00216305:26230/07:PU70806!RIV08-MSM-26230___
n4:strany
676-679
n4:aktivita
n7:P n7:Z
n4:aktivity
P(GD102/05/H050), Z(MSM0021630528)
n4:dodaniDat
n17:2008
n4:domaciTvurceVysledku
n6:9452591 n6:4123484 n6:7825668 n6:1196332 n6:5518288
n4:druhVysledku
n13:D
n4:duvernostUdaju
n19:S
n4:entitaPredkladatele
n14:predkladatel
n4:idSjednocenehoVysledku
439526
n4:idVysledku
RIV/00216305:26230/07:PU70806
n4:jazykVysledku
n10:eng
n4:klicovaSlova
Communication Protocol Testing, Fault Tolerant Systems, Checker, FPGA, VHDL
n4:klicoveSlovo
n11:Communication%20Protocol%20Testing n11:VHDL n11:FPGA n11:Checker n11:Fault%20Tolerant%20Systems
n4:kontrolniKodProRIV
[11E1045FA648]
n4:mistoKonaniAkce
Lübeck
n4:mistoVydani
Lubeck, Germany
n4:nazevZdroje
10th EUROMICRO Conference on Digital System Design DSD 2007
n4:obor
n18:JC
n4:pocetDomacichTvurcuVysledku
5
n4:pocetTvurcuVysledku
5
n4:projekt
n16:GD102%2F05%2FH050
n4:rokUplatneniVysledku
n17:2007
n4:tvurceVysledku
Straka, Martin Kořenek, Jan Kotásek, Zdeněk Martínek, Tomáš Tobola, Jiří
n4:typAkce
n15:WRD
n4:zahajeniAkce
2007-08-27+02:00
n4:zamer
n9:MSM0021630528
s:numberOfPages
4
n22:hasPublisher
IEEE Computer Society
n12:isbn
0-7695-2978-X
n21:organizacniJednotka
26230