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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F05%3APU56493%21RIV06-GA0-26230___
rdf:type
n14:Vysledek skos:Concept
dcterms:description
Článek se zabývá možnostmi nástroje Scan Educational Tool sloužícím k výuce principů tzv. scan techniky. Ve článku jsou představeny všechny moduly a režimy činnosti nástroje a nastíněny směry jeho možného využití ve výuce. In the paper, the principles of Scan Educational Tool are presented. First, the motivation for this activity is briefly mentioned. Then, the structure of software package together with the principles of communicating and controlling the tools belonging to the system are explained. It is shown how the system can be utilized for testability analysis and design for testability demonstrations resulting in applying scan design principles in the design. In the paper, the principles of Scan Educational Tool are presented. First, the motivation for this activity is briefly mentioned. Then, the structure of software package together with the principles of communicating and controlling the tools belonging to the system are explained. It is shown how the system can be utilized for testability analysis and design for testability demonstrations resulting in applying scan design principles in the design.
dcterms:title
Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies Výukový nástroj pro demonstraci principů scan technik v oblasti návrhu pro snadnou testovatelnost
skos:prefLabel
Výukový nástroj pro demonstraci principů scan technik v oblasti návrhu pro snadnou testovatelnost Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies
skos:notation
RIV/00216305:26230/05:PU56493!RIV06-GA0-26230___
n3:strany
420-427
n3:aktivita
n12:P
n3:aktivity
P(GA102/04/0737), P(GP102/05/P193)
n3:dodaniDat
n8:2006
n3:domaciTvurceVysledku
n11:8821968 n11:7825668
n3:druhVysledku
n6:D
n3:duvernostUdaju
n16:S
n3:entitaPredkladatele
n21:predkladatel
n3:idSjednocenehoVysledku
519143
n3:idVysledku
RIV/00216305:26230/05:PU56493
n3:jazykVysledku
n4:eng
n3:klicovaSlova
scan, scan layout selection, testability, design for testability, register-transfer level, automatization, genetic algorithm, feedback loops, design constraints, trade-off
n3:klicoveSlovo
n7:scan n7:design%20constraints n7:design%20for%20testability n7:register-transfer%20level n7:testability n7:feedback%20loops n7:trade-off n7:genetic%20algorithm n7:scan%20layout%20selection n7:automatization
n3:kontrolniKodProRIV
[A624E7DE8035]
n3:mistoKonaniAkce
Faculdade de Engenharia da Universidade do Porto
n3:mistoVydani
Los Alamitos
n3:nazevZdroje
Proceedings of 8th Euromicro Conference on Digital System Design
n3:obor
n13:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:projekt
n18:GA102%2F04%2F0737 n18:GP102%2F05%2FP193
n3:rokUplatneniVysledku
n8:2005
n3:tvurceVysledku
Kotásek, Zdeněk Strnadel, Josef
n3:typAkce
n19:WRD
n3:zahajeniAkce
2005-06-13+02:00
s:numberOfPages
8
n17:hasPublisher
IEEE Computer Society
n20:isbn
0-7695-2433-8
n15:organizacniJednotka
26230