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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F05%3APU56455%21RIV10-MSM-26230___
rdf:type
skos:Concept n21:Vysledek
dcterms:description
The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too. The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too.
dcterms:title
High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design
skos:prefLabel
High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design
skos:notation
RIV/00216305:26230/05:PU56455!RIV10-MSM-26230___
n3:aktivita
n10:P n10:Z
n3:aktivity
P(GA102/04/0780), P(GA102/05/0723), Z(MSM6383917201)
n3:dodaniDat
n6:2010
n3:domaciTvurceVysledku
n11:9761985 n11:1458841 n11:1842919
n3:druhVysledku
n5:D
n3:duvernostUdaju
n16:S
n3:entitaPredkladatele
n20:predkladatel
n3:idSjednocenehoVysledku
523308
n3:idVysledku
RIV/00216305:26230/05:PU56455
n3:jazykVysledku
n22:eng
n3:klicovaSlova
formal analysis and verification, timed automata, parametric analysis, FPGA, hardware, computer networks<br>
n3:klicoveSlovo
n9:computer%20networks%3Cbr%3E n9:parametric%20analysis n9:timed%20automata n9:FPGA n9:formal%20analysis%20and%20verification n9:hardware
n3:kontrolniKodProRIV
[427F43B23673]
n3:mistoKonaniAkce
Saarbruecken
n3:mistoVydani
Berlin
n3:nazevZdroje
Correct Hardware Design and Verification Methods
n3:obor
n12:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n15:GA102%2F04%2F0780 n15:GA102%2F05%2F0723
n3:rokUplatneniVysledku
n6:2005
n3:tvurceVysledku
Smrčka, Aleš Vojnar, Tomáš Matoušek, Petr
n3:typAkce
n4:WRD
n3:zahajeniAkce
2005-10-03+02:00
n3:zamer
n18:MSM6383917201
s:numberOfPages
5
n13:hasPublisher
Springer-Verlag
n14:isbn
978-3-540-29105-3
n17:organizacniJednotka
26230