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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F05%3APU55722%21RIV06-GA0-26230___
rdf:type
skos:Concept n16:Vysledek
dcterms:description
The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematiical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model. The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematiical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model. Článek se zabývá analýzou datové cesty číslicového obvodu na úrovni meziregistrových přenosů a využitím jejích výsledků ve vybraných oblastech diagnostiky číslicových systémů. Metoda je založena na tzv. virtuálních portech, konstrukci dvojice speciálníchorientovaných grafů (graf datového toku testovacích vzorků, graf datového toku odezev) a jejich analýze.
dcterms:title
VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements VIRTA: Analýza a zlepšení testovatelnosti založená na virtuálních portech VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements
skos:prefLabel
VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements VIRTA: Analýza a zlepšení testovatelnosti založená na virtuálních portech
skos:notation
RIV/00216305:26230/05:PU55722!RIV06-GA0-26230___
n3:strany
190-193
n3:aktivita
n17:P
n3:aktivity
P(GA102/04/0737), P(GP102/05/P193)
n3:dodaniDat
n11:2006
n3:domaciTvurceVysledku
n13:8821968
n3:druhVysledku
n8:D
n3:duvernostUdaju
n18:S
n3:entitaPredkladatele
n5:predkladatel
n3:idSjednocenehoVysledku
548869
n3:idVysledku
RIV/00216305:26230/05:PU55722
n3:jazykVysledku
n7:eng
n3:klicovaSlova
Testability analysis, data-path, register-transfer level, transparency, I-path concept, virtual port, digraph, test-pattern data-flow digraph, test-response data-flow digraph, graph algorithm, design for testability, scan, benchmark circuit.
n3:klicoveSlovo
n10:graph%20algorithm n10:test-pattern%20data-flow%20digraph n10:transparency n10:test-response%20data-flow%20digraph n10:I-path%20concept n10:register-transfer%20level n10:benchmark%20circuit. n10:digraph n10:virtual%20port n10:Testability%20analysis n10:design%20for%20testability n10:scan n10:data-path
n3:kontrolniKodProRIV
[00B965877FB7]
n3:mistoKonaniAkce
Sopron
n3:mistoVydani
Sopron
n3:nazevZdroje
Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop
n3:obor
n15:JC
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
1
n3:projekt
n14:GA102%2F04%2F0737 n14:GP102%2F05%2FP193
n3:rokUplatneniVysledku
n11:2005
n3:tvurceVysledku
Strnadel, Josef
n3:typAkce
n19:WRD
n3:zahajeniAkce
2005-04-13+02:00
s:numberOfPages
4
n21:hasPublisher
University of West Hungary
n20:isbn
963-9364-48-7
n12:organizacniJednotka
26230