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Statements

Subject Item
n2:RIV%2F00216305%3A26230%2F04%3APU49175%21RIV06-MSM-26230___
rdf:type
n6:Vysledek skos:Concept
dcterms:description
This article describes the design of the lookup machine implemented in hardware accelerator COMBO6 for IPv6 and IPv4 packet routing. The lookup machine is a single instruction machine using Content Addressable and Static Memories and the operations are performed by Field Programmable Gate Arrays. The design of the lookup machine is difficult to be proven correct by conventional methods, therefore model checking as a method of formal verification was employed and this case is explained in detail. In thee last part, the article sums up software support needed to make behavior of the accelerator equivalent to the host computer. Tento článek popisuje návhr vyhledávacího stroje implementovaného v hardwarovém akcelerátoru COMBO6 pro IPv6 a IPv4 směrování.<br> This article describes the design of the lookup machine implemented in hardware accelerator COMBO6 for IPv6 and IPv4 packet routing. The lookup machine is a single instruction machine using Content Addressable and Static Memories and the operations are performed by Field Programmable Gate Arrays. The design of the lookup machine is difficult to be proven correct by conventional methods, therefore model checking as a method of formal verification was employed and this case is explained in detail. In thee last part, the article sums up software support needed to make behavior of the accelerator equivalent to the host computer.
dcterms:title
Hardwarový vyhledávací stroj a jeho formální verifikace Hardware Router's Lookup Machine and its Formal Verification Hardware Router's Lookup Machine and its Formal Verification
skos:prefLabel
Hardware Router's Lookup Machine and its Formal Verification Hardwarový vyhledávací stroj a jeho formální verifikace Hardware Router's Lookup Machine and its Formal Verification
skos:notation
RIV/00216305:26230/04:PU49175!RIV06-MSM-26230___
n3:strany
1002-1007
n3:aktivita
n8:Z
n3:aktivity
Z(MSM6383917201)
n3:dodaniDat
n14:2006
n3:domaciTvurceVysledku
n9:9452591
n3:druhVysledku
n20:D
n3:duvernostUdaju
n10:S
n3:entitaPredkladatele
n5:predkladatel
n3:idSjednocenehoVysledku
565930
n3:idVysledku
RIV/00216305:26230/04:PU49175
n3:jazykVysledku
n16:eng
n3:klicovaSlova
IPv6 routing, FPGA, formal verification, Liberouter
n3:klicoveSlovo
n4:formal%20verification n4:IPv6%20routing n4:FPGA n4:Liberouter
n3:kontrolniKodProRIV
[E244B748D881]
n3:mistoKonaniAkce
Gosier, Guadeloupe
n3:mistoVydani
Colmar
n3:nazevZdroje
Proceedings of the 3rd International Conference on Networking ICN '04
n3:obor
n21:JC
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
2
n3:rokUplatneniVysledku
n14:2004
n3:tvurceVysledku
Kořenek, Jan Antoš, David
n3:typAkce
n13:WRD
n3:zahajeniAkce
2004-02-29+01:00
n3:zamer
n19:MSM6383917201
s:numberOfPages
6
n18:hasPublisher
University of Haute Alsace
n7:isbn
0-86341-325-0
n17:organizacniJednotka
26230